A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface high-speed DRAM interface

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 193-194

  Bae, Seung Jun ^a   Sohn, Young Soo ^a   Oh, Tae Young ^a   Kwak, Sang Hyup ^a   Kim, Dong Min ^a   Kim, Dae Hyun ^a   Kim, Young Sik ^a   Yang, Yoo Seok ^a   Doo, Su Yeon ^a   Lee, Jin Il ^a   Bang, Sam Young ^a   Park, Sun Young ^a   Yeom, Ki Woong ^a   Lee, Jae Young ^a   Park, Hwanwook ^a   Kim, Woo Seop ^a   Yang, Hyang Ja ^a   Park, Kwang Il ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK TREE; CLOSED LOOPS; HIGH-FREQUENCY NOISE; HIGH-SPEED; INTEGRATION METHOD; LOW JITTERS; OFF-CHIP; ON CHIPS; RANDOM JITTERS; REDUCTION TECHNIQUES; SINGLE-ENDED;

DYNAMIC RANDOM ACCESS STORAGE; INTEGRATION; JITTER; TRANSCEIVERS;

VLSI CIRCUITS;

EID: 77958013444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560300     Document Type: Conference Paper

References (6)

1. Seung-Jun Bae, et al, "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques," IEEE ISSCC, pp.278-613, Feb. 2008
2. N. Nguyen, et al, "A 16-Gb/s Differential I/O Cell with 380fs RJ in Emulated 40nm DRAM process," in Symp. VLSI Circuits, Dig. Tech. Papers, pp.128-129, Jun. 2008
3. Berny, A.D., et al, "A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration," IEEE JSSC, pp. 909-917, April 2005
4. Thomas Toifl, et al., "A Small-Area Voltage Regulator with High-Bandwidth Supply-Rejection Using a Regulated Replica in 45nm CMOS SOI," IEEE ASSCC, pp. 157-160, 2008
5. Park, M., et al, "A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver," IEEE ISSCC, pp.230-599, Feb. 2007
6. HungWen Lu; et al, "A Scalable Digitalized Buffer for Gigabit I/O," IEEE TCAS-II, pp.1026-1030, Oct. 2008