Spur-free all-digital PLL in 65nm for mobile phones

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 52-53

  Staszewski, Robert Bogdan ^a   Waheed, Khurram ^b   Vemulapalli, Sudheer ^b   Dulger, Fikret ^b   Wallberg, John ^b   Hung, Chih Ming ^b   Eliezer, Oren ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE LOCKED LOOPS; PHASE NOISE;

BLUETOOTH RADIO; DIGITAL ACTIVITIES; DIGITALLY CONTROLLED OSCILLATORS; INJECTION PULLING; TIME AND FREQUENCIES; TIME TO DIGITAL CONVERTERS; TRADITIONAL APPROACHES; WIRELESS STANDARDS;

FREQUENCY CONVERTERS;

EID: 79955737362     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746215     Document Type: Conference Paper

References (8)

1. B. Staszewski et al., "All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 272-273, Feb. 2004.
2. R. B. Staszewski et al., "All-digital PLL and GSM/EDGE transmitter in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 316-317, 600, Feb. 2005.
3. C.-M. Hsu et al., "A low-noise, wide-BW 3.6GHz digital ΔΣ fract.-N frequency synthesizer with a noise-shaping TDC and quantization noise cancellation," ISSCC Dig. Tech. Papers, pp. 340-341, Feb. 2008.
4. H.-H. Chang et al., "A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE," ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2008.
5. C. Weltin-Wu et al., "A 3GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," ISSCC Dig. Tech. Papers, pp. 344-345, Feb. 2008.
6. C. Weltin-Wu et al., "A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation," ISSCC Dig. Tech. Papers, pp. 468-469, Feb. 2010.
7. R. Staszewski et al., "Elimination of spurious noise due to time-to-digital converter," IEEE Dallas Circuits and Systems Workshop, pp. 67-70, Oct. 2009.
8. S. D. Vamvakos et al., "Noise analysis of time-to-digital converter in all-digital PLLs," IEEE Dallas Circ. and Sys. Workshop, pp. 87-90, Oct. 2009.