A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 468-469

  Weltin Wu, Colin ^a,b   Temporiti, Enrico ^c   Baldi, Daniele ^c   Cusmai, Marco ^b   Svelto, Francesco ^b  

^a Och Spine at New York Presbyterian Hospitals   (United States)

^b UNIVERSITY OF PAVIA   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; FEED-FORWARD COMPENSATION; FRACTIONAL SPURS; FREQUENCY SYNTHESIS; HIGH RESOLUTION; IN-BAND; IN-BAND PHASE NOISE; NANOSCALE CMOS; NOISE IMMUNITY; NON-LINEARITY; PROGRAMMABILITY; SAMPLED DATA SYSTEMS; SPURIOUS TONES; WIDE-BAND; WIDEBAND WIRELESS;

PHASE NOISE; SAMPLED DATA CONTROL SYSTEMS; SYNTHESIS (CHEMICAL);

TRANSMITTERS;

EID: 77952162660     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433846     Document Type: Conference Paper

References (6)

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4. M. Lee, M. Heidari, A. Abidi, "A Low Noise, Wideband Digital Phase-locked Loop based on a New Time-to-Digital Converter with Subpicosecond Resolution," VLSI Dig. Tech. Papers, pp.112-113, June 2008
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