A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 476-477

  Zanuso, Marco ^a   Levantino, Salvatore ^a   Samori, Carlo ^a   Lacaita, Andrea ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CANCELLATION ALGORITHMS; FEEDBACK PHASE; FRACTIONAL-N; FRACTIONAL-N SYNTHESIZER; PHASE ERROR; PHASE INTERPOLATOR; QUANTIZATION NOISE; SPUR CANCELLATION; TIME TO DIGITAL CONVERTERS;

FEEDBACK LINEARIZATION; FREQUENCY CONVERTERS;

PHASE LOCKED LOOPS;

EID: 77952137361     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433842     Document Type: Conference Paper

References (5)

1. C. Hsu, M. Z. Straayer, M. H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," ISSCC Dig. Tech. Papers, pp. 340-341, 2008.
2. H. Chang, et al., "A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE," ISSCC Dig. Tech. Papers, pp. 200-201, 2008.
3. C. Weltin-Wu, et al., "A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction," ISSCC Dig. Tech. Papers, pp. 344-345, 2008.
4. C.-H. Park, O. Kim, and B. Kim, "A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching," IEEE J. of Solid-State Circuits, pp. 777-783, May 2001.
5. R. B. Staszewski, et al., "All-Digital PLL and Transmitter for Mobile Phones," IEEE J. of Solid-State Circuits, pp. 2469-2482, Dec. 2005.