A 2.2GHz sub-sampling PLL with 0.16psrms Jitter and -125dBc/Hz in-band phase noise at 700μW loop-components power

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 139-140

  Gao, Xiang ^a   Klumperink, Eric ^a   Socci, Gerard ^b   Bohsali, Mounir ^b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IN-BAND PHASE NOISE; PHASE DETECTORS; POWER EFFICIENT; REFERENCE CLOCK; SUB-SAMPLING;

ANTENNA PHASED ARRAYS; JITTER; PHASE NOISE; SWITCHING CIRCUITS; TRANSMITTERS; VARIABLE FREQUENCY OSCILLATORS;

VLSI CIRCUITS;

EID: 77956224145     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560323     Document Type: Conference Paper

References (4)

1. rms jitter in 0.18μm CMOS," ISSCC, pp. 392 - 393, Feb. 2009.
2. X. Gao, et al., "Spur-Reduction Techniques for PLLs Using Sub-Sampling Phase Detection," ISSCC, paper 26.4, Feb. 2010.
3. B. Helal, et al., "A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop," J. Solid-State Circuits, pp.1391-1400, May 2009.
4. J. Lee and H. Wang, "Study of subharmonically injection-locked PLLs," J. Solid-State Circuits, pp.1539-1553, May 2009.