Silicon nanowire all-around gate MOSFETs built on a bulk substrate by all plasma-etching routes

IEEE Electron Device Letters

Volumn 32, Issue 4, 2011, Pages 452-454

  Moon, Dong Il ^a   Choi, Sung Jin ^a   Kim, Chung Jin ^a   Kim, Jee Yeon ^a   Lee, Jin Seong ^a   Oh, Jae Sub ^b   Lee, Gi Sung ^b   Park, Yun Chang ^b   Hong, Dae Won ^b   Lee, Dong Wook ^b   Kim, Young Su ^b   Kim, Jeoung Woo ^b   Han, Jin Woo ^a   Choi, Yang Kyu ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b National Nano Fab Center (NNFC)   (South Korea)

Author keywords

All around gate (AAG); Bosch process; bulk MOSFET; deep reactive ion etch; gate all around; plasma etching; short channel effects (SCEs); silicon nanowire (SiNW)

Indexed keywords

ALL-AROUND GATE; BOSCH PROCESS; BULK MOSFET; DEEP REACTIVE-ION ETCH; GATE-ALL-AROUND; SHORT-CHANNEL EFFECTS (SCES); SILICON NANOWIRE (SINW);

ELECTRIC WIRE; IONS; MOSFET DEVICES; NANOWIRES; PLASMA ETCHING; SEMICONDUCTING SILICON COMPOUNDS;

REACTIVE ION ETCHING;

EID: 79953052385     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2106758     Document Type: Article

References (10)

1. S. Bangsaruntip, G.M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann, N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillorn, T. Barwicz, L. Sekaric, M. M. Frank, and J. W. Sleight, "High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling," in IEDM Tech. Dig., 2009, pp. 297-300.
2. Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, "High performance silicon nanowire field effect transistors," Nano Lett., vol. 3, no. 2, pp. 149-152, Jan. 2003. (Pubitemid 37130527)
3. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "High-performance fully depleted silicon nanowire (Diameter ≥ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-385, May 2006.
4. S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C.W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "High performance 5 nm radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720. (Pubitemid 46370951)
5. K. E. Moselund, P. Dobrosz, S. Olsen, V. Pott, L. De Michielis, D. Tsamados, D. Bouvet, A. O'Neill, and A. M. Ionescu, "Bended gateall-around nanowire MOSFET: A device with enhanced carrier mobility due to oxidation-induced tensile stress," in IEDM Tech. Dig., 2007, pp. 191-194.
6. Y. Tian, R. Huang, Y. Wang, J. Zhuge, R. Wang, J. Liu, X. Zhang, and Y.Wang, "New self-aligned silicon nanowire transistors on bulk substrate fabricated by epi-free compatible CMOS technology: Process integration, experimental characterization of carrier transport and low frequency noise," in IEDM Tech. Dig., 2007, pp. 895-898.
7. R. M. Y. Ng, T. Wang, F. Liu, X. Zuo, J. He, and M. Chan, "Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation," IEEE Electron Device Lett., vol. 30, no. 5, pp. 520-522, May 2009.
8. V. Pott, K. E. Moselund, D. Bouvet, L. De Michielis, and A. M. Ionescu, "Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon," IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 733-744, Nov. 2008.
9. K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, "Patterning sub-30-nm MOSFET gate with I-line lithography," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1004-1006, May 2001. (Pubitemid 32444266)
10. S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, "Universality of short-channel effects in undoped-body silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 31, no. 9, pp. 903-905, Sep. 2010.