Post-silicon bug detection for variation induced electrical bugs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 273-278

  Gao, Ming ^a   Lisherness, Peter ^a   Cheng, Kwang Ting ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-FLIPS; BUG DETECTION; CORRELATION FACTORS; DESIGN-FOR-DEBUG; ERROR EFFECT; FUNCTIONAL SIMULATIONS; FUNCTIONAL TEST; INJECTION TECHNIQUES; MODELING TECHNIQUE; NOISE MARGINS; OBSERVATION POINT; POST-SILICON; POWER DROOP; SIMULATION-BASED; TIMING DETAILS; VALIDATION TEST;

FLIP FLOP CIRCUITS;

COMPUTER AIDED DESIGN;

EID: 79952945081     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722197     Document Type: Conference Paper

References (10)

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