New challenges in delay testing of nanometer, multigigahertz designs

IEEE Design and Test of Computers

Volumn 21, Issue 3, 2004, Pages 241-247

  Mak, T M ^a   Krstic, Angela ^b   Cheng, Kwang Ting Tim ^c   Wang, Li C ^c  

^a INTEL CORPORATION   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP-SUBMICRON DESIGN; DEEP-SUBMICRON TECHNOLOGY; DELAY TESTING; STATIC TIMING ANALYSIS; TRANSITION FAULT TESTING;

BUILT-IN SELF TEST; COMPUTER SIMULATION; DELAY CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; STATISTICAL METHODS;

TIMING CIRCUITS;

EID: 3042539155     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.17     Document Type: Article

References (12)

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