A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 101-102

  Musa, Ahmed ^a   Murakami, Rui ^a   Sato, Takahiro ^a   Chaivipas, Win ^a   Okada, Kenichi ^a   Matsuzawa, Akira ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; INJECTION TECHNIQUES; MEASUREMENT RESULTS; PLL FREQUENCY SYNTHESIZER; TUNING RANGES;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FREQUENCY SYNTHESIZERS;

PHASE NOISE;

EID: 79952941688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722158     Document Type: Conference Paper

References (6)

1. K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, "A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS," in ISSCC, 2009, pp. 494-495,495a.
2. A. Musa, R. Murakami, T. Sato, W. Chiavipas, K. Okada, and A. Matsuzawa, "A 58-63.6ghz quadrature pll frequency synthesizer in 65nm cmos," in ASSCC, 2010, p. (In press).
3. K.-H. Tsai, J.-H.Wu, and S.-I. Liu, "A Digitally Calibrated 64.3-66.2GHz Phase-Locked Loop," in RFIC, June 2008, pp. 307-310.
4. C. Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu, "A 50.8-53GHz Clock Generator Using a Harmonic-Locked PD in 0.13um CMOS," TCASII, vol. 55, no. 5, pp. 404-408, May 2008.
5. C. Lee and S. L. Liu, "A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS," in ISSCC, 2007, pp. 196-596.
6. H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, and R. Fujimoto, "A 60-GHz Phase-Locked Loop with Inductor-less Prescaler in 90-nm CMOS," in ESS-CIRC, 2007, pp. 472-475.