A 58-63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Volumn , Issue , 2010, Pages 189-192

  Musa, Ahmed ^a   Murakami, Rui ^a   Sato, Takahiro ^a   Chiavipas, Win ^a   Okada, Kenichi ^a   Matsuzawa, Akira ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; INJECTION LOCKED OSCILLATORS; LOCKING RANGE; MEASUREMENT RESULTS; PLL FREQUENCY SYNTHESIZER; TUNING RANGES;

CMOS INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; OSCILLATORS (ELECTRONIC);

PHASE NOISE;

EID: 79952834200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2010.5716587     Document Type: Conference Paper

References (12)

1. K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, "A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS," in ISSCC, 2009, pp. 494-495,495a.
2. O. Lee, J.-G. Kim, K. Lim, J. Laskar, and S. Hong, "A 60-GHz push-push InGaP HBT VCO with Dynamic Frequency Divider," MWCL, vol. 15, no. 10, pp. 679-681, Oct. 2005.
3. T. Nakamura, T. Masuda, K. Washio, and H. Kondoh, "A 59GHz push-push VCO with 13.9GHz Tuning Range using Loop-Ground Transmission Line for a Full-Band 60GHz Transceiver," in ISSCC, 2009, pp. 496-497.
4. B. Catli and M. Hella, "A 60 GHz CMOS Combined mm-wave VCO/Divider with 10-GHz Tuning Range," in CICC, 2009, pp. 665-668.
5. S. Hara, K. Okada, and A. Matsuzawa, "A 9.3MHz to 5.7GHz Tunable LC-based VCO Using a Divide-by-N Injection-Locked Frequency Divider," in ASSCC, 2009, pp. 81-84.
6. C. Lee and S. L. Liu, "A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS," in ISSCC, 2007, pp. 196-596.
7. H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, and R. Fujimoto, "A 60-GHz Phase-Locked Loop with Inductor-less Prescaler in 90-nm CMOS," in ESSCIRC, 2007, pp. 472-475.
8. W. Chan and J. Long, "A 56-65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS," JSSC, vol. 43, no. 12, pp. 2739-2746, Dec. 2008.
9. B. Razavi, "A Study of Injection Locking and Pulling in Oscillators," JSSC, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.
10. K.-H. Tsai, J.-H. Wu, and S.-I. Liu, "A Digitally Calibrated 64.3-66.2GHz Phase-Locked Loop," in RFIC, June 2008, pp. 307-310.
11. C. Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu, "A 50.8-53GHz Clock Generator Using a Harmonic-Locked PD in 0.13um CMOS," TCASII, vol. 55, no. 5, pp. 404-408, May 2008.
12. C. Cao, Y. Ding, and K. O, "A 50-GHz Phase-Locked Loop in 130-nm CMOS," in CICC, 2006, pp. 21-24.