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Volumn , Issue , 2011, Pages 105-108

A 350 μW 2.3 GHz integer-N frequency synthesizer for body area network applications

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; BODY AREA NETWORK; INTEGER-N; LOW POWER; OUTPUT FREQUENCY; POWER CONSUMPTION; PRESCALERS; QUADRATURE VCO; REFERENCE SPUR; SUPPLY VOLTAGES;

EID: 79952840082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIRF.2011.5719342     Document Type: Conference Paper
Times cited : (2)

References (12)
  • 2
    • 77649170237 scopus 로고    scopus 로고
    • A 0.6-V Zero-IF/Low-IF Receiver with Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications
    • A. Balankutty, Y. Shih-An, F. Yiping, and P. R. Kinget, "A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications," Solid-State Circuits, IEEE Journal of, vol. 45, no. 3, pp. 538-553, 2010.
    • (2010) Solid-State Circuits, IEEE Journal of , vol.45 , Issue.3 , pp. 538-553
    • Balankutty, A.1    Shih-An, Y.2    Yiping, F.3    Kinget, P.R.4
  • 6
    • 0030188644 scopus 로고    scopus 로고
    • A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
    • J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS," Solid-State Circuits, IEEE Journal of, vol. 31, no. 7, pp. 890-897, 1996.
    • (1996) Solid-State Circuits, IEEE Journal of , vol.31 , Issue.7 , pp. 890-897
    • Craninckx, J.1    Steyaert, M.S.J.2
  • 7
    • 0030828211 scopus 로고    scopus 로고
    • New single-clock CMOS latches and flipflops with improved speed and power savings
    • J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings," Solid-State Circuits, IEEE Journal of, vol. 32, no. 1, pp. 62-69, 1997.
    • (1997) Solid-State Circuits, IEEE Journal of , vol.32 , Issue.1 , pp. 62-69
    • Yuan, J.1    Svensson, C.2
  • 11
    • 75149137298 scopus 로고    scopus 로고
    • A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-μm CMOS
    • P. W. Park, D. Park, and S. H. Cho, "A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-μm CMOS," Microwave and Wireless Components Letters, IEEE, vol. 20, no. 1, pp. 52-54, 2010.
    • (2010) Microwave and Wireless Components Letters, IEEE , vol.20 , Issue.1 , pp. 52-54
    • Park, P.W.1    Park, D.2    Cho, S.H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.