A 100 MHz ladder feRAM design with capacitance-coupled-bitline (CCB) cell

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 3, 2011, Pages 681-689

  Takashima, Daisaburo ^a   Nagadomi, Yasushi ^a   Ozaki, Tohru ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Disturbance; embedded; FeRAM; ferroelectric memory; logic process; reliability

Indexed keywords

DISTURBANCE; EMBEDDED; FERAM; FERROELECTRIC MEMORY; LOGIC PROCESS;

CAPACITANCE; CAPACITORS; CELLS; FERROELECTRIC DEVICES; FERROELECTRICITY; LADDERS; RANDOM ACCESS STORAGE;

CYTOLOGY;

EID: 79952056680     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2098210     Document Type: Article

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