An 8kB EEPROM-emulation dataFLASH module for automotive MCU

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 507-509

  Kawai, Shinji ^a   Hosogane, Akira ^a   Kuge, Shigehiro ^a   Abe, Toshihiro ^a   Hashimoto, Kohei ^a   Oishi, Tsukasa ^a   Tsuji, Naoki ^a   Sakakibara, Kiyohiko ^a   Noguchi, Kenji ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; MICROCONTROLLERS;

CHANNEL STRUCTURES; CHIP ARCHITECTURE; FLASH MEMORY CELL; HIGH RELIABILITY; MODULE DESIGN; PROGRAM/ERASE; READ CHANNELS; SEPARATED CHANNELS;

MEMORY ARCHITECTURE;

EID: 49549098406     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523280     Document Type: Conference Paper

References (2)

1. N. Tsuji, N. Ajika, K. Yuzuriha et al., "New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characteristics," IEDM Dig. Tech. Papers, pp. 53-54, Dec. 1994.
2. S. Yamada, Y. Hiura, T. Yamane et al., "Degradation Mechanism of Flash EEPROM Programming After Program/Erase Cycles," IEDM Dig. Tech. Papers, pp. 23-26, Dec. 1993.