Analysis of execution efficiency in the microthreaded processor UTLEON3

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6566 LNCS, Issue , 2011, Pages 110-121

  Sykora, Jaroslav ^a   Kafka, Leos ^a   Danek, Martin ^a   Kohout, Lukas ^a  

^a INSTITUTE OF INFORMATION THEORY AND AUTOMATION   (Czech Republic)

Author keywords

execution efficiency; memory latency tolerance; micro threading; multi threading; Processor architectures; SVP concurrency model; UTLEON3 processor

Indexed keywords

EXECUTION EFFICIENCY; MEMORY LATENCIES; MICRO-THREADING; MULTI-THREADING; PROCESSOR ARCHITECTURES; SVP CONCURRENCY MODEL; UTLEON3 PROCESSOR;

ARCHITECTURE; MEMORY ARCHITECTURE; OPTIMIZATION; PROGRAM COMPILERS;

PIPELINE PROCESSING SYSTEMS;

EID: 79952036320     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-19137-4_10     Document Type: Conference Paper

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