Design of a comparator tree based on reversible logic

2010 10th IEEE Conference on Nanotechnology, NANO 2010

Volumn , Issue , 2010, Pages 1113-1116

  Thapliyal, Himanshu ^a   Ranganathan, Nagarajan ^a   Ferreira, Ryan ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY TREE STRUCTURE; BIT NUMBERS; COMPARISON RESULT; INTERNAL NODES; LOGIC EQUATIONS; NOT GATE; OUTPUT CIRCUITS; QUANTUM COSTS; REVERSIBLE GATES; REVERSIBLE LOGIC; ROOT NODES; TOFFOLI GATES; TREE-BASED;

BINARY TREES; DESIGN; LOGIC GATES; MATHEMATICAL OPERATORS; NANOTECHNOLOGY; TREES (MATHEMATICS);

COMPARATORS (OPTICAL);

EID: 79951837289     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2010.5697872     Document Type: Conference Paper

References (10)

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