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Proceedings - Third International Conference on Natural Computation, ICNC 2007

Volumn 5, Issue , 2007, Pages 180-184

Dynamically reconfigurable cache for low-power embedded system

(4) Chen, Liming a Zou, Xuecheng a Lei, Jianming a Liu, Zhenglin a

a HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASSOCIATIVE STORAGE; BENCHMARKING; BUFFER STORAGE; COMPUTER SIMULATION; ENERGY UTILIZATION;

AUTOMATICALLY SEARCHING; RECONFIGURATION MANAGEMENT ALGORITHM; SPEC CPU2000;

EMBEDDED SYSTEMS;

EID: 38049003050 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICNC.2007.346 Document Type: Conference Paper

Times cited : (29)

References (7)

1
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- D.H. Albonesi, "Selective Cache Ways: On Demand Cache Resource Allocation", IEEE/ACM International Symposium on Microarchitecture (MICRO-32), pp. 248-259, 1999.
- (1999) IEEE/ACM International Symposium on Microarchitecture (MICRO-32) , pp. 248-259
- Albonesi, D.H.¹

2
- 0036863795
- Platune: A Tuning Framework for System-on-a-chip Platforms
- Nov
- T. Givargis, and F. Vahid, "Platune: A Tuning Framework for System-on-a-chip Platforms", IEEE Transactions on Computer Aided Design (TCAD), Vol. 21(11), pp. 1317-1327, Nov. 2002.
- (2002) IEEE Transactions on Computer Aided Design (TCAD) , vol.21 , Issue.11 , pp. 1317-1327
- Givargis, T.¹ Vahid, F.²

3
- 0034461413
- Memory Hierarchy Reconfiguration for Energy and Performance in General-purpose Processor Architectures
- Dec
- R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, "Memory Hierarchy Reconfiguration for Energy and Performance in General-purpose Processor Architectures", In 33rd International Symposium on Microarchitecture, pp. 245-257, Dec. 2000.
- (2000) 33rd International Symposium on Microarchitecture , pp. 245-257
- Balasubramonian, R.¹ Albonesi, D.H.² Buyuktosunoglu, A.³ Dwarkadas, S.⁴

4
- 0035693947
- Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct Mapping
- M. Powell, A. Agaewal, T. Vijaykumar, B. Falsafi, and K. Roy, "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct Mapping", Int. Symposium on Microarchitecture, 2001.
- (2001) Int. Symposium on Microarchitecture
- Powell, M.¹ Agaewal, A.² Vijaykumar, T.³ Falsafi, B.⁴ Roy, K.⁵

5
- 0035425547
- A Reconfigurable Multi-function Computing Cache Architecture
- Aug
- H. Kim, A.K. Somani, and A. Tyagi, "A Reconfigurable Multi-function Computing Cache Architecture", IEEE Transactions on VLSI, Vol. 9, No. 4, pp. 509-523, Aug. 2001.
- (2001) IEEE Transactions on VLSI , vol.9 , Issue.4 , pp. 509-523
- Kim, H.¹ Somani, A.K.² Tyagi, A.³

6
- 0033656195
- A Low Power Unified Cache Architecture Providing Power and Performance Flexibility
- Jun
- A. Malik, B. Moyer and D. Cermak. "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility", International Symposium on Low Power Electronics and Design, pp. 241-243, Jun. 2000.
- (2000) International Symposium on Low Power Electronics and Design , pp. 241-243
- Malik, A.¹ Moyer, B.² Cermak, D.³

7
- 84948961559
- Energy Efficient Frequent Value Data Cache Design
- Nov
- J. Yang, and R. Gupta, "Energy Efficient Frequent Value Data Cache Design", Int. Symp. on Microarchitecture, pp. 197-207, Nov. 2002.
- (2002) Int. Symp. on Microarchitecture , pp. 197-207
- Yang, J.¹ Gupta, R.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.