COGRE: A configuration memory reduced reconfigurable logic cell architecture for area minimization

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 304-309

  Okamoto, Yasuhiro ^a   Ichinomiya, Yoshihiro ^a   Amagasaki, Motoki ^a   Iida, Masahiro ^a   Sueyoshi, Toshinori ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

Author keywords

Field programmable gate array; Logic cell; NPN equivalence

Indexed keywords

AREA MINIMIZATION; CIRCUIT IMPLEMENTATION; CONFIGURATION MEMORY; FPGAS AND ASICS; LOGIC CELL; LOGIC CELLS; LOGIC FUNCTIONS; NAND GATE; NOT GATE; NPN-EQUIVALENCE; PROGRAMMABLE INVERTER; RECONFIGURABLE LOGIC CELLS; REDUNDANCY FACTORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUNCTIONS; LOGIC GATES; MEMORY ARCHITECTURE; SET THEORY;

EQUIVALENCE CLASSES;

EID: 79951758484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.68     Document Type: Conference Paper

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