ERCBench: An open-source benchmark suite for embedded and reconfigurable computing

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 408-413

  Chang, Daniel W ^a   Jenkins, Christipher D ^a   Garcia, Philip C ^a   Gilani, Syed Z ^a   Aguilera, Paula ^a   Nagarajan, Aishwarya ^a   Anderson, Michael J ^a   Kenny, Matthew A ^a   Bauer, Sean M ^a   Schulte, Michael J ^a   Compton, Katherine ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Benchmarks; Embedded computing; Open source; Reconfigurable computing

Indexed keywords

APPLICATION AREA; BENCHMARK SUITES; BENCHMARKS; CONTROL FLOWS; EMBEDDED COMPUTING; HARDWARE ACCELERATORS; HARDWARE/SOFTWARE; MULTIMEDIA PROCESSING; OPEN-SOURCE; RECONFIGURABLE COMPUTING; SOFTWARE-BASED; VERILOG; WIRELESS COMMUNICATIONS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; RESEARCH; WIRELESS TELECOMMUNICATION SYSTEMS;

BENCHMARKING;

EID: 79951728853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.85     Document Type: Conference Paper

References (21)

1. J. L. Henning, "SPEC CPU2006 benchmark descriptions," ACM SIGARCH Computer Architecture News, vol. 34, pp. 1-17, 2006.
2. J. A. Poovey, T. M. Conte, M. Levy, and S. Gal-On "A Benchmark Characterization of the EEMBC Benchmark Suite," IEEE Micro, vol. 29, no.5, pp.18-29, Sept.-Oct. 2009
3. M. R. Guthaus, J.S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," IEEE Workshop on Workload Characterization, pp. 184-193, 2001.
4. C. Lee, M. Potkonjak, W. H. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems," ACM/IEEE International Symposium on Microarchitecture, pp. 330-335, 1997.
5. J. E. Fritts, F. W. Steiling, J. A. Tucek and W. Wolf, "MediaBench II video: Expediting the next generation of videosystems research," Microprocessors and Microsystems, 2009.
6. I. Antochi, B. Juurlink, S. Vassiliadis and P. Liuha, "GraalBench: A 3D graphics benchmark suite for mobile phones," ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 1-9, 2004.
7. J. Babb, M. Frank, V. Lee, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni and A. Agarwal, "The RAW benchmark suite: computation structures for general purpose computing," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 161-171, 1997.
8. S. Kumar, L. Pires, S. Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, H. Spaanenberg, "A benchmark suite for evaluating configurable computing systems - status, reflections, and future directions," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 126-134, 2000.
9. OpenCores, 2010. [Online] Available: http://www.opencores.org.
10. OpenFPGA, 2010. [Online] Available: http://www.openfpga.org.
11. P. Jamieson, T. Becker, P. Y. K. Cheung, W. Luk, T. Rissa and T. Pitkänen, "Benchmarking and evaluating reconfigurable architectures targeting the mobile domain," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 15, pp. 1-24, 2010.
12. UMass RCG HDL Benchmark Collection, 2006. [Online] Available: http://www.ecs.umass.edu/ece/tessier/rcg/benchmarks.
13. S. Yang, "Logic synthesis and optimization benchmarks user guide version 3.0," Tech. Report, Microelectronics Center of North Carolina, Jan, 1991.
14. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," Lecture Notes in Computer Science, vol. 1304, pp. 213-222, 1997. (Pubitemid 127118755)
15. fpgaCAD, 2010. [Online] Available: http://fpgacad.ece.wisc.edu/.
16. G. Kahn and D. B. MacQueen, "Coroutines and networks of parallel programming," Information Processing, vol. 77, pp. 993-998, 1977.
17. A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier and M. Wrighton, "Design patterns for reconfigurable computing," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 13-23, 2004. (Pubitemid 40661978)
18. W. Fu and K. Compton, "A simulation platform for reconfigurable computing research," in Field Programmable Logic and Applications, 2006. FPL'06. International Conference on, pp. 1-7, 2006.
19. P. Garcia and K. Compton, "Kernel sharing on reconfigurable multiprocessor systems," Internatinoal Conference on Field-Programmable Technology, pp. 225-232, 2008.
20. D. A. El-Dib and M. I. Elmasry, "Modified register-exchange Viterbi decoder for low-power wireless communications," IEEE Transactions on Circuits and Systems I, vol. 51, pp. 371-378, 2004.
21. J. Cho, S. Mirzaei, J. Oberg and R. Kastner, "FPGA-based face detection system using Haar classifiers," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 103-112, 2009.