FPGA-Based face detection system haar classifiers

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 103-111

  Cho, Junguk ^a   Mirzaei, Shahnam ^b   Oberg, Jason ^b   Kastner, Ryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

Author keywords

AdaBoost; Architecture; Design; Experimentation; Face detection; FPGA; Haar classifier; Measurement; Performance; Processing; Real time

Indexed keywords

ADABOOST; EXPERIMENTATION; FACE DETECTION; FPGA; HAAR CLASSIFIER; PERFORMANCE; REAL-TIME;

ADAPTIVE BOOSTING; CLASSIFIERS; FACE RECOGNITION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LEARNING SYSTEMS; LOGIC GATES; PIPELINE PROCESSING SYSTEMS;

ARCHITECTURAL DESIGN;

EID: 67650702527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508144     Document Type: Conference Paper

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