A monitoring system for NoCs

3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43

Volumn , Issue , 2010, Pages 25-30

  Fiorin, Leandro ^a   Palermo, Gianluca ^b   Silvano, Cristina ^b  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

hardware counters; networks on chip; performance monitoring; systems on chip

Indexed keywords

DESIGN CHALLENGES; DYNAMIC CHANGES; EXECUTION TIME; HARDWARE COUNTERS; MONITORING ARCHITECTURE; MONITORING SYSTEM; MULTIMEDIA APPLICATIONS; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORKS ON CHIPS; NETWORKS-ON-CHIP; PERFORMANCE MONITORING; RUNTIMES; SYSTEM BEHAVIORS; SYSTEM INFORMATION; SYSTEMS-ON-CHIP; TRAFFIC OVERHEAD;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BEHAVIORAL RESEARCH; DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; PROGRAM DEBUGGING;

MONITORING;

EID: 79951643194     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1921249.1921257     Document Type: Conference Paper

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