A multi-core debug platform for NoC-based systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 870-875

  Tang, Shan ^a,b   Xu, Qiang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); SYNCHRONIZATION;

CORES UNDER DEBUG (CUD); GIGASCALE INTEGRATED CIRCUITS; NETWORK-ON-CHIP (NOC);

PROGRAM DEBUGGING;

EID: 34548361505     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364402     Document Type: Conference Paper

References (22)

1. K. M. Al-Tawil, M. Abd-El-Barr, and F. Ashraf. A Survey and Comparison of Wormhole Routing Techniques in a Mesh Networks. IEEE Network, 11(2):38-45, Mar-Apr 1997.
2. Altera Inc. Design Debugging Using the SignalTap II Embedded Logic Analyzer, http://www.altera.com.
3. ARM Ltd. AMBA AXI Protocol Specification. http://www.arm.com.
4. ARM Ltd. How CoreSight Technology Gets Higher Performance, More Reliable Product to Market Quicker. http://www.arm.com.
5. L. Benini and G. de Micheli. Networks on chips: A new SoC paradigm. Computer, 12(1):70-78, 2002.
6. T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Comput. Surv., 38(1):1-54, 2006.
7. C. Ciordaş, et al. An event-based monitoring service for networks on chip. ACM TODAES, 10(4):702-723, 2005.
8. C. Ciordaş, et al. Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective. In Proc. IEEE IES, 2006.
9. W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. DAC, pp. 18-22, 2001.
10. K. Goossens, J. Dielissen, and A. Radulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design & Test of Computers, 22(5):21-31, 2005.
11. A. B. T. Hopkins and K. D. McDonald-Maier. Debug Support for Complex Systems on-Chip: A Review. IEE PCDT, 153(4): 197-207, 2006.
12. R. Leatherman and N. Stollon. An Embedded Debugging Architecture for SOCs. IEEE Potentials, 24(1): 12-16, 2005.
13. MIPS Technologies Inc. EJTAG Trace Control Block Specification. http://www.mips.com.
14. OCP International Partnership. Open Core Protocol Specification. http://www.ocpip.org.
15. Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification, http://www.philips.com.
16. Semiconductor Industry Association (SIA). The International Technology Roadmap for Semiconductors (ITRS): 2003 Edition.
17. N. Stollon et al. Multi-Core Embedded Debug for Structured ASIC Systems. In Proc. DesignCon, 2004.
18. B. Vermeulen and S. K. Goel. Design for Debug: Catching Design Errors in Digital Chips. IEEE Design & Test of Computers, 19(3):35-43, 2002.
19. B. Vermeulen, T. Waayers, and S. Bakker. IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. In Proc. ITC, pp. 55-63, 2002.
20. B. Vermeulen, T. Waayers, and S. K. Goel. Core-Based Scan Architecture for Silicon Debug. In Proc. ITC, pp. 638-647, 2002.
21. Xilinx Inc. Chipscope Pro Software and Cores User Guide. http://www.xilinx.com.
22. Q. Xu and N. Nicolici. Resource-Constrained System-on-a-Chip Test: A Survey. IEE PCDT, 152(1):67-81, 2005.