Debugging distributed-shared-memory communication at multiple granularities in networks on chip

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 3-12

  Vermeulen, Bart ^a   Goossens, Kees ^a,b   Umrani, Siddharth ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED-SHARED-MEMORY; NARROWCAST CONNECTIONS; NETWORKS ON CHIP (NOC);

COMPUTER HARDWARE; DEMULTIPLEXING; DISTRIBUTED COMPUTER SYSTEMS; INTERNET PROTOCOLS; SOFTWARE ENGINEERING;

PROGRAM DEBUGGING;

EID: 44149114053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492720     Document Type: Conference Paper

References (19)

1. ARM. AMBA AXI Protocol Specification, June 2003.
2. C. Ciordaş, T. Basten, A. Rǎdulescu, K. Goossens, and J. van Meerbergen. An event-based monitoring service for networks on chip. ACM Transactions on Design Automation of Electronic Systems. Oct 2005.
3. C. Ciordaş, K. Goossens, T. Basten, A. Rädulescu, and A. Boon. Transaction monitoring in networks on chip: The on-chip run-time perspective. In Proc. Symposium on Industrial Embedded Systems (IES), Oct 2006.
4. P. Dahlgren, P. Dickinson, and I. Parulkar. Latch Divergency in Microprocessor Failure Analysis. In Proc. IEEE Int'l Test Conference, Sep/Oct 2003.
5. S. K. Goel and B. Vermeulen. Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips. In Proc. IEEE Int'l Test Conference (ITC), Oct 2002.
6. S. González Pestana, E. Rijpkema, A. Rädulescu, K. Goossens, and O. P. Gangwal. Cost-performance trade-offs in networks on chip: A simulation-based approach. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb 2004.
7. K. Goossens, J. Dielissen, and A. Rädulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, Sept/Oct 2005.
8. K. Goossens, B. Vermeulen, R. van Steeden, and M. Bennebroek. Transaction-based communication-centric debug. In Proc. Int'l Symposium on Networks on Chip (NOCS), May 2007.
9. A. Hansson and K. Goossens. Trade-offs in the configuration of a network on chip for multiple use-cases. In Proc. Int'l Symposium on Networks on Chip (NOCS), May 2007.
10. K. Holdbrook, S. Joshi, S. Mitra, J. Petolino, R. Raman, and M. Wong. microSPARC: A case study of scan-based debug. In Proc. IEEE Int'l Test Conference (ITC), 1994.
11. A. Hopkins and K. McDonald-Maier. Debug support for complex systems on-chip: A review. IEE Proc. Computers and Digital Techniques, July 2006.
12. R. Leatherman and N. Stollon. An embedded debugging architecture for SoCs. IEEE Potentials, Feb-Mar 2005.
13. OCP International Partnership. Open core protocol specification, 2001.
14. Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification. Version 2.2, July 2002.
15. G. Rootselaar and B. Vermeulen. Silicon Debug: Scan Chains Alone Are Not Enough. In Proc. IEEE Int'l Test Conference (ITC), Sept. 1999.
16. A. Rǎdulescu, J. Dielissen, S. González Pestana, O. P. Gangwal, E. Rijpkema, P. Wielage, and K. Goossens. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Transactions on CAD of Integrated Circuits and Systems, Jan 2005.
17. S. Tang and Q. Xu. A multi-core debug platform for NoC-based systems. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2007.
18. B. Vermeulen, K. Goossens, R. van Steeden, and M. Bennebroek. Communication-centric SOC debug using transactions. In Proc. European Test Symposium (ETS), May 2007.
19. B. Vermeulen, T Waayers, and S. Goel. Core-based Scan Architecture for Silicon Debug. In Proc. IEEE Int'l Test Conference (ITC), Oct 2002.