Chemical mechanical planarization of copper bumps on printed circuit board

International Journal of Precision Engineering and Manufacturing

Volumn 12, Issue 1, 2011, Pages 149-152

  Jeong, Moonki ^a   Jo, Seungjae ^a   Lee, Hyunseop ^a   Lee, Ahreum ^a   Kang, Chungyun ^a   Choi, Jinwon ^b   Kim, Jinho ^b   Jeong, HaeDo ^a  

^a Pusan National University   (South Korea)

^b Samsung Electro Mechanics   (South Korea)

Author keywords

CMP; Cu Bump; Flip Chip; PCB; Polishing; Printed Circuit board

Indexed keywords

EID: 79751479312     PISSN: 12298557     EISSN: None     Source Type: Journal    
DOI: 10.1007/s12541-011-0019-6     Document Type: Article

References (12)

1. Freudenberg Mektec Europa GmbH, Flexible Printed Circuits Open Up a Multitude of Innovative Applications, http://www.pcb007.com
2. de Jong, E. C. W., Ferreira, B. J. A. and Bauer, P., Toward the Next Level of PCB Usage in Power Electronic Converters, IEEE Transactions on Power Electronics, Vol. 23, No. 6, pp. 3151-3163, 2008.
3. Hok, G. B., A Study of High Speed implementation for System on Chip on 2 layers Printed Circuit Board, Integrated Circuits, ISIC '07, pp. 150-153, 2007.
4. Wolf, M. J., Engelmann, G., Dietrich, L. and Reichl, H., Flip chip bumping technology-Status and update, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 565, No. 1, pp. 290-295, 2006.
5. Lee, J.-T., Won, J.-K. and Lee, E.-S., A study on the characteristics of a wafer-polishing process according to machining conditions, Int. J. Precis. Eng. Manuf., Vol. 10, No. 1, pp. 23-28, 2009.
6. Park, S.-W., Kim, C.-B., Kim, S.-Y. and Seo, Y.-J., Design of experimental optimization for ULSI CMP process applications, Microelectronic Engineering, Vol. 66, No. 1-4, pp. 488-495, 2003.
7. Du, T., Vijayakumar, A. and Desai, V., Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions, Electrochimica Acta, Vol. 49, No. 25, pp. 4505-4512, 2004.
8. Seo, Y. J., Lee, W. S., Kim, S. Y., Park, J. S. and Chang, E. G., Optimization of post-CMP cleaning process for elimination of CMP slurry-induced metallic contaminations, J. Mater. Sci. Mater. Electron., Vol. 12, No. 7, pp. 411-415, 2001.
9. Venkatesh, V. C., Inasaki, I., Toenshof, H. K., Nakagawa, T. and Marinescu, I. D., Observations on Polishing and Ultraprecision Machining of Semiconductor Substrate Materials, CIRP Annals - Manufacturing Technology, Vol. 44, No. 2, pp. 611-618, 1995.
10. Monteith, M. P. and Parekh, N., Components of within-wafer non-uniformity in a dielectric CMP process, Proc. CMP-MIC, pp. 169-172, 1997.
11. Fu, G. and Chandra, A., The relationship between wafer surface pressure and wafer backside loading in Chemical Mechanical Polishing, Thin Solid Films, Vol. 474, No. 1-2, pp. 217-221, 2005.
12. Pandija, S., Roy, D. and Babu, S. V., Achievement of high planarization efficiency in CMP of copper at a reduced down pressure, Microelectronic Engineering, Vol. 86, No. 3, pp. 367-373, 2009.