A charge recycling TCAM with checkerboard array arrangement for low power applications

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 253-256

  Kusumoto, Takahito ^a   Ogawa, Daisuke ^a   Dosaka, Katsumi ^a   Miyama, Masayuki ^a   Matsuda, Yoshio ^a  

^a KANAZAWA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE RECYCLING; CONVENTIONAL DESIGN; LOW NOISE; LOW POWER; LOW POWER APPLICATION; MATCH LINE; POWER CONSUMPTION; POWER LINE NOISE; POWERFUL ENGINES; SEARCH LINES; TERNARY CONTENT ADDRESSABLE MEMORIES;

ELECTRIC LINES; RECYCLING; TELECOMMUNICATION LINES;

LOGIC GATES;

EID: 67649983300     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708776     Document Type: Conference Paper

References (12)

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