A power-efficient wide-range phase-locked loop

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 1, 2002, Pages 51-62

  Chen, Oscal T C ^a,b   Sheen, Robin Ruey Bin ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

Clock generator; Low power; Phase locked loop; Voltage controlled oscillator

Indexed keywords

CHARGE PUMP; CLOCK GENERATION; LOOP FILTER; PHASE-FREQUENCY DETECTOR;

CMOS INTEGRATED CIRCUITS; DETECTOR CIRCUITS; ELECTRIC FILTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY DIVIDING CIRCUITS; JITTER; THRESHOLD VOLTAGE; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 0036175856     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.974545     Document Type: Article

References (17)

1. The VLSI Handbook
2. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
3. A 320MHz, 1.5 mW @ 1.35V CMOS PLL for microprocessor clock generation
4. Design of low-jitter 1-GHz phase-locked loops for digital clock generation
5. DD capability
6. A fast CMOS voltage-controlled ring oscillator
7. Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment
8. A 3.3V 600MHz-1.30GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects
9. A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range
10. A wide-range phase-locked loop using a range-programmable voltage-controlled oscillator
11. A low power, wide linear-range CMOS voltage-controlled oscillator
12. A 0.25μm CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range
13. A wide-bandwidth low-voltage PLL for PowerPC™ microprocessors
14. Accurately calculate PLL charge pump filter parameters