-
1
-
-
35648995516
-
-
(UCB/EECS-2006-183), December
-
Krste Asanovic, Ras Bodik, Bryan C. Catanzaro, Joseph J. Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William L. Plishker, John Shalf, Samuel W. Williams, and Katherine A. Yelick. The landscape of parallel computing research: a view from berkeley. (UCB/EECS-2006-183), December 2006.
-
(2006)
The Landscape of Parallel Computing Research: A View from Berkeley
-
-
Asanovic, K.1
Bodik, R.2
Catanzaro, B.C.3
Gebis, J.J.4
Husbands, P.5
Keutzer, K.6
Patterson, D.A.7
Plishker, W.L.8
Shalf, J.9
Williams, S.W.10
Yelick, K.A.11
-
2
-
-
0033891806
-
Fast template placement for reconfigurable computing systems
-
jan-mar
-
K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast template placement for reconfigurable computing systems. Design Test of Computers, IEEE, 17(1):68-83, jan-mar 2000.
-
(2000)
Design Test of Computers, IEEE
, vol.17
, Issue.1
, pp. 68-83
-
-
Bazargan, K.1
Kastner, R.2
Sarrafzadeh, M.3
-
4
-
-
0036149420
-
Networks on chips: A new soc paradigm
-
Jan
-
L. Benini and G. De Micheli. Networks on chips: a new soc paradigm. Computer, 35(1):70-78, Jan 2002.
-
(2002)
Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
5
-
-
63549095070
-
The parsec benchmark suite: Characterization and architectural implications
-
October
-
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. The parsec benchmark suite: characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pages 72-81, October 2008.
-
(2008)
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques
, pp. 72-81
-
-
Bienia, C.1
Kumar, S.2
Singh, J.P.3
Li, K.4
-
10
-
-
84944322013
-
A two-step genetic algorithm for mapping task graphs to a network on chip architecture
-
Washington, DC, USA, IEEE Computer Society
-
Tang Lei and Shashi Kumar. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In DSD '03: Proceedings of the Euromicro Symposium on Digital Systems Design, page 180, Washington, DC, USA, 2003. IEEE Computer Society.
-
(2003)
DSD '03: Proceedings of the Euromicro Symposium on Digital Systems Design
, pp. 180
-
-
Lei, T.1
Kumar, S.2
-
11
-
-
0036469676
-
Simics: A full system simulation platform
-
February
-
P.S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. Computer, 35(2):50-58, February 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.S.1
Christensson, M.2
Eskilson, J.3
Forsgren, D.4
Hallberg, G.5
Hogberg, J.6
Larsson, F.7
Moestedt, A.8
Werner, B.9
-
12
-
-
34548862331
-
Evaluation of algorithms for low energy mapping onto nocs
-
C.A.M. Marcon, E.I. Moreno, N.L.V. Calazans, and F.G. Moraes. Evaluation of algorithms for low energy mapping onto nocs. In Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007, pages 389-392, 2007.
-
(2007)
Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007
, pp. 389-392
-
-
Marcon, C.A.M.1
Moreno, E.I.2
Calazans, N.L.V.3
Moraes, F.G.4
-
13
-
-
33746910637
-
Mapping and configuration methods for multi-use-case networks on chips
-
Piscataway, NJ, USA, IEEE Press
-
Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, and Giovanni De Micheli. Mapping and configuration methods for multi-use-case networks on chips. In ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference, pages 146-151, Piscataway, NJ, USA, 2006. IEEE Press.
-
(2006)
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
, pp. 146-151
-
-
Murali, S.1
Coenen, M.2
Radulescu, A.3
Goossens, K.4
De Micheli, G.5
-
14
-
-
78751491619
-
-
University of Catania
-
University of Catania. Noxim. http://www.noxim.org/.
-
-
-
-
15
-
-
0002375353
-
The splash-2 programs: Characterization and methodological considerations
-
0
-
Jaswinder Pal Singh, Anoop Gupta, Moriyoshi Ohara, Evan Torrie, and Steven Cameron Woo. The splash-2 programs: Characterization and methodological considerations. Computer Architecture, International Symposium on, 0:24, 1995.
-
(1995)
Computer Architecture, International Symposium on
, pp. 24
-
-
Singh, J.P.1
Gupta, A.2
Ohara, M.3
Torrie, E.4
Woo, S.C.5
-
16
-
-
78751489027
-
-
Tpc-h
-
TPC. Tpc-h. http://www.tpc.org/tpch/.
-
-
-
-
17
-
-
85008053864
-
An 80-tile sub-100-w teraflops processor in 65-nm cmos
-
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits, IEEE Journal of, 43(1):29-41, 2008.
-
(2008)
Solid-State Circuits, IEEE Journal of
, vol.43
, Issue.1
, pp. 29-41
-
-
Vangal, S.R.1
Howard, J.2
Ruhl, G.3
Dighe, S.4
Wilson, H.5
Tschanz, J.6
Finan, D.7
Singh, A.8
Jacob, T.9
Jain, S.10
Erraguntla, V.11
Roberts, C.12
Hoskote, Y.13
Borkar, N.14
Borkar, S.15
-
18
-
-
77954946006
-
Tree-model based mapping for energy-efficient and low-latency network-on-chip
-
14-16
-
Bo Yang, Thomas Canhao Xu, Tero Santti, and Juha Plosila. Tree-model based mapping for energy-efficient and low-latency network-on-chip. In Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 189 -192, 14-16 2010.
-
(2010)
Design and Diagnostics of Electronic Circuits and Systems (DDECS)
, pp. 189-192
-
-
Yang, B.1
Xu, T.C.2
Santti, T.3
Plosila, J.4
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