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Journal of Korean Institute of Metals and Materials

Volumn 48, Issue 11, 2010, Pages 1041-1046

Retardation of massive spalling by palladium layer addition to surface finish

(3) Lee, Dae Hyun a,b Chung, Bo Mook a,c Huh, Joo Youl a

a Korea University (South Korea)

b SAMSUNG Electronics (South Korea)

c KPMTECH (South Korea)

Author keywords

Electronic matrials; Microstructure; Palladium surface finish; Scanning electron microscopy; Soldering

Indexed keywords

BULK SOLDER; CONSUMPTION RATES; CU SUBSTRATE; ELECTROLESS; ELECTROLESS NI; ELECTRONIC MATRIALS; LAYER THICKNESS; MOLTEN SOLDERS; PALLADIUM LAYERS; PD ATOMS; REDUCED GROWTH RATE; RETARDING EFFECT; SN-3.0AG-0.5CU; SOLDER ALLOYS; SURFACE FINISHES; THIN-LAYER DEPOSITION;

COPPER ALLOYS; DEPOSITION; FINISHING; GOLD; GOLD COATINGS; MICROSTRUCTURE; SCANNING ELECTRON MICROSCOPY; SOLDERED JOINTS; SOLDERING; SOLDERING ALLOYS; SPALLING;

TIN;

EID: 78650907150 PISSN: 17388228 EISSN: None Source Type: Journal
DOI: 10.3365/KJMM.2010.48.11.1041 Document Type: Article

Times cited : (12)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.