Speculative Thread Execution in a Multithreaded Dataflow Architecture

19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006

Volumn , Issue , 2006, Pages 102-107

  Li, Wentong ^a   Kavi, Krishna ^a   Naz, Afrin ^a   Sweany, Phil ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW ANALYSIS; MULTITASKING; PARALLEL PROCESSING SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

BRANCH PREDICTION; DATA-FLOW ARCHITECTURES; INSTRUCTION LEVEL PARALLELISM; MULTITHREADED; OUT-OF-ORDER EXECUTION; SCALAR PROCESSORS; SPECULATIVE EXECUTION; THREAD LEVEL SPECULATION; VALUE PREDICTION; VLIW PROCESSOR;

PROGRAM COMPILERS;

EID: 78650847755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D. Burger. “Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures”, 27th International Symposium on Computer Architecture (ISCA), pp.248-259, June 2000.
2. K. Sankaralingam, R. Nagarajan, H. Liu, J. Huh, C.K. Kim, D. Burger, S.W. Keckler, and C.R Moore. “Exploiting ILP, TLP, and DLP Using Polymorphism in the TRIPS Architecture”, 30th International Symposium on Computer Architecture (ISCA), pp. 422-433, June 2003.
3. S. Swanson, K. Michelson, A. Schwerin, and M. Os-kin. “WaveScalar”, In Proceedings of the 36th International Symposium on Microarchitecture(MICRO), pp291-302, December 2003.
4. K.M. Kavi. H.S. Kim and A.R. Hurson. “Scheduled dataflow architecture: A synchronous execution paradigm for dataflow”, IASTED Journal of Computers andApplications, pp114-124, Vol. 21, No. 3 (Oct. 1999).
5. K.M. Kavi, R. Giorgi and J. Arul. “Scheduled Dataflow: Execution paradigm, architecture and performance evolution”, IEEE Transactions on Computers, pp 834-846, Vol. 50, No. 8, August 2001.
6. D.M. Tullsen, S.J. Eggers, H.M. Levy, and J.L. Lo, “Simultaneous multithreading: Maximizing on-chip parallelism”, In International. Symposium on Computer Architecture (ISCA), pp. 392-403, June 1995.
7. M. Franklin and G.S. Sohi. “ABR: A Hardware Mechanism for Dynamic Reordering of Memory References”, IEEE Transactions on Computers, Vol. 50, No. 5, May 1996.
8. P. Marcuello, A. Gonzalez and J.Tubella. “Speculative Multithreaded Processors”, In proceeding of the International Conference on Supercomputing, pages 77-84, July 1998.
9. Y. Zhang, L. Rauchwerger, and J. Torrelas. “Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors”, In 5th International Symposium on High-Performance Computer Architecture (HPCA), pp.135-141, January 1999.
10. J.G. Steffan, C.B. Colohan, A. Zhai, and T.C. Mowry,”A Scalable Approach to Thread-Level Speculation”, 27th International Symposium on Computer Architecture (ISCA), pp.1-12, June 2000.
11. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach (3rd edition),2003.
12. A.R. Hurson, J.T. Lim, K.M. Kavi, and B. Lee, “Parallelization of DOALL and DOACROSS Loops - A Survey”, Advances in Computers, pp.53-103, Vol. 45, 1997
13. K.M. Lepak and M.H. Lipasi, “On the Value Locality of Store Instructions”, 27th International Symposium on Computer Architecture (ISCA), pp.182-191, June 2000.