Scheduled dataflow architecture: A synchronous execution paradigm for dataflow

International Journal of Computers and Applications

Volumn 21, Issue 3, 1999, Pages 114-124

  Kavi, Krishna M ^a,c,d   Kim, Hyong Shik ^a,e   Hurson, Ali R ^b  

^a UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

^c UNIVERSITY OF TEXAS AT ARLINGTON   (United States)

^d NATIONAL SCIENCE FOUNDATION   (United States)

^e Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

SCHEDULED DATAFLOW ARCHITECTURE;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA FLOW ANALYSIS; RESPONSE TIME (COMPUTER SYSTEMS);

PIPELINE PROCESSING SYSTEMS;

EID: 0033284073     PISSN: 1206212X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (20)

1. A.R. Hurson, K.M. Kavi, & B. Lee, Cache memories in dataflow architectures, IEEE Parallel and Dist. Tech., Winter 1996, 50-64.
2. K.M. Kavi et al., Design of cache memories for multi-threaded dataflow architecture, Proc. 22nd Int. Symp. on Comp. Arch. (ISCA-22), June 1995, St. Margherita Ligure, Italy, 253-264.
3. M. Takesue, A unified resource management and execution control mechanism for Dataflow Machines, Proc 14th Annual Int. Symp. on Camp. Arch., June 1987, 90-97.
4. S.A. Thoreson & A.N Long, A feasibility study of a memory hierarchy in data flow environment, Proc. Int Conf on Parallel Conj., June 1987, 356-360
5. M. Tokoro, J.R. Jagannathan, & H. Sunahara, On the working set concept for data-flow machines, Proc. 10th Int. Symp. on Camp. Arch., July 1983, 90-97.
6. R. Govindarajan, S.S. Namawarkar. & P. LeNir. Design and performance evaluation of a multithreaded architecture, Proc, of the HPCA-1, Jan. 1995, 298-307.
7. H.H.-J. Hum. The super-actor machine; A hyörid dataflow/von Neumann architecture. Ph.D thesis, McGill University, Montreal, Que., Canada, May 1992.
8. S. Sakai et al., Super-threading: Architectural and software mechanisms for optimizing parallel computations, Proc. 1993 Int. Conf. or. Supercomputing, July 1993, 251-260.
9. G.M. Papadopolous & D.E. Culler, Monsoon: An explicit token-store architecture, 17th Int. Symp. on Comp. Arch., June 1990, 82-90.
10. H.H.-J. Hum et al., A design study of the EARTH multiprocessor, Proc. Conf on Parallel Architectures and Compilation Tech., Limassol, Cyprus, June 1995, 59-68.
11. J.E. Smith, Decoupled access/execute computer architectures, Proc 9th Annual Symp. on Camp. Arch., May 1982, 112-119.
12. A. Agarwal et al., The MIT Alewife machine: architecture and performance, Proc, 22nd Int. Symp. on Comp, Arch. (ISCA-22), 1995, 2-13.
13. D. Chiou et al., StarT-NG: Delivering seamless parallel computing, Proc. 1st Int. EURO-PAR Conference, Aug. 1995, 101-116.
14. K.M. Kavi, D. Levine, & A.R. Hurson, PL/PS: A non-blockiog multithreaded architecture, Proc. 5th Int. Conf. on Adv. Comp.(ADCOMP '97), Madras, India, Dec. 1997.
15. K.M. Kavi &: A.R. Hurson, Investigation of operand memory reuse in a dynamic dataflow architecture, Proc. High Performance Computing Symp. 96, April 8-11, 1996, New Orleans, Louisiana, 288-295.
16. H.-S. Kim, Instruction set architecture of Scheduled Dataflow, Technical Report, Dept. of Electrical and Computer Engineering. University of Alabama in Huntsville, April 1998.
17. A. Agarwal, Performance tradeoffs in multithreaded processors, IEEE Trans, on Parallel and Distr. Sys., 3(5), September 1992, 525-539.
18. D.E. Culler, Multithreading: Fundamental limits. potential gains and alternatives, Proc. Supercomputing 91, Workshop on Multithreading, 1992.
19. J.L. Hennessy & D.A. Patterson, Computer architecture: A quantitative approach (Morgan Kaufmann Publisher, 1996), 105.
20. A. Agarwal et al., Sparcle: An evolutionary processor design for multiprocessors, IEEE Micro, June 1993, 48-61.