Cache configuration exploration on prototyping platforms

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2003-January, Issue , 2003, Pages 164-170

  Zhang, Chuanjun ^a   Vahid, F ^a,b  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Application specific integrated circuits; Computer architecture; Computer science; Embedded computing; Embedded system; Memory architecture; Microprocessors; Prototypes; Testing; Virtual prototyping

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SCIENCE; EMBEDDED SYSTEMS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PARETO PRINCIPLE; TESTING; VIRTUAL PROTOTYPING;

CACHE ARCHITECTURE; CACHE CONFIGURATIONS; EMBEDDED COMPUTING; PARETO-OPTIMAL SETS; POWER OVERHEAD; PROTOTYPES; PROTOTYPING PLATFORM; WAY PREDICTION;

COMPUTER ARCHITECTURE;

EID: 78650732949     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWRSP.2003.1207044     Document Type: Conference Paper

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