MPEG macroblock parsing and pel reconstruction on an FPGA-augmented TriMedia processor

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 425-430

  Sima, Mihai ^a,b   Cotofana, Sorin ^a   Vassiliadis, Stamatis ^a   Van Eijndhoven, Jos T J ^b   Vissers, Kees ^c  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c TriMedia Technologies Inc   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; FIELD PROGRAMMABLE GATE ARRAYS; MOTION PICTURES;

VARIABLE-LENGTH DECODERS (VLD);

PROGRAM PROCESSORS;

EID: 0035188081     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955061     Document Type: Article

References (13)

1. A high performance microarchitecture with hardware-programmable functional units
2. Garp: A MIPS processor with a reconfigurable coprocessor
3. ConCISe: A compiler-driven CPLD-based instruction set accelerator
4. TriMedia CPU64 architecture
5. Architecture of FPGAs and CPLDs: A tutorial
6. A time-multiplexed FPGA
7. A taxonomy of custom computing machines
8. TriMedia CPU64 application development environment
9. 8 × 8 IDCT implementation on an FPGA-augmented TriMedia