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Volumn , Issue , 2010, Pages 135-144

Improving platform-based system synthesis by satisfiability Modulo theories solving

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC SYSTEMS; EARLY LEARNING; LINEAR CONSTRAINTS; NETWORK DESIGN; NON-FUNCTIONAL; NON-LINEAR CONSTRAINTS; PARTIAL IMPLEMENTATION; PERFORMANCE ANALYSIS; PLATFORM BASED DESIGN; RUNTIMES; SATISFIABILITY MODULO THEORIES; STRINGENT CONSTRAINTS; SYSTEM COMPLEXITY; SYSTEM SYNTHESIS; TIMING CONSTRAINTS;

EID: 78650672427     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1878961.1878986     Document Type: Conference Paper
Times cited : (25)

References (23)
  • 2
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    • CVC Lite: A new implementation of the cooperating validity checker
    • C. Barrett and S. Berezin. CVC Lite: A New Implementation of the Cooperating Validity Checker. In Proc. of CAV '04, pages 515-518, 2004.
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    • Barrett, C.1    Berezin, S.2
  • 4
    • 84919401135 scopus 로고
    • A machine program for theorem-proving
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    • (1962) Comm. of the ACM , vol.5 , Issue.7 , pp. 394-397
    • Davis, M.1    Logemann, G.2    Loveland, D.3
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    • 33749846787 scopus 로고    scopus 로고
    • A fast linear-arithmetic solver for DPLL(T)
    • B. Dutertre and L. de Moura. A Fast Linear-Arithmetic Solver for DPLL(T). In Proc. of CAV '06, pages 81-94, 2006.
    • (2006) Proc. of CAV '06 , pp. 81-94
    • Dutertre, B.1    De Moura, L.2
  • 8
    • 9644281035 scopus 로고    scopus 로고
    • Methods for evaluating and covering the design space during early design development
    • M. Gries. Methods for Evaluating and Covering the Design Space During Early Design Development. Integration, The VLSI Journal, 38(2):131-183, 2004.
    • (2004) Integration, the VLSI Journal , vol.38 , Issue.2 , pp. 131-183
    • Gries, M.1
  • 11
    • 84880778172 scopus 로고    scopus 로고
    • A structure-based variable ordering heuristic for SAT
    • J. Huang and A. Darwiche. A Structure-based Variable Ordering Heuristic for SAT. In Proc. of IJCAI '03, pages 1167-1172, 2003.
    • (2003) Proc. of IJCAI '03 , pp. 1167-1172
    • Huang, J.1    Darwiche, A.2
  • 14
    • 35048827513 scopus 로고    scopus 로고
    • The UCLID decision procedure
    • S. K. Lahiri and S. A. Seshia. The UCLID Decision Procedure. In Proc. of CAV '04, pages 475-478, 2004.
    • (2004) Proc. of CAV '04 , pp. 475-478
    • Lahiri, S.K.1    Seshia, S.A.2
  • 15
  • 17
    • 0031096921 scopus 로고    scopus 로고
    • An algorithm for hardware/software partitioning using mixed Integer Linear Programming
    • R. Niemann and P. Marwedel. An algorithm for hardware/software partitioning using mixed Integer Linear Programming. Design Automation for Embedded Systems, 2(2):165-193, 1997.
    • (1997) Design Automation for Embedded Systems , vol.2 , Issue.2 , pp. 165-193
    • Niemann, R.1    Marwedel, P.2
  • 18
    • 26444452555 scopus 로고    scopus 로고
    • DPLL(T) with exhaustive theory propagation and its application to difference logic
    • R. Nieuwenhuis and A. Oliveras. DPLL(T) with Exhaustive Theory Propagation and Its Application to Difference Logic. In Proc. of CAV '05, pages 321-334, 2005.
    • (2005) Proc. of CAV '05 , pp. 321-334
    • Nieuwenhuis, R.1    Oliveras, A.2
  • 21
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    • Mapping applications to tiled multiprocessor embedded systems
    • L. Thiele, I. Bacivarov, W. Haid, and K. Huang. Mapping Applications to Tiled Multiprocessor Embedded Systems. In Proc. of ACSD '07, pages 29-40, 2007.
    • (2007) Proc. of ACSD '07 , pp. 29-40
    • Thiele, L.1    Bacivarov, I.2    Haid, W.3    Huang, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.