System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design

Eurasip Journal on Embedded Systems

Volumn 2008, Issue 1, 2008, Pages

  Dömer, Rainer ^a   Gerstlauer, Andreas ^a   Peng, Junyu ^a   Shin, Dongwan ^a   Cai, Lukai ^a   Yu, Haobo ^a   Abdi, Samar ^a   Gajski, Daniel D ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 49749151366     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/2008/647953     Document Type: Article

References (32)

1. Gajski D. D., Zhu J., Dömer R., Gerstlauer A., Zhao S., SpecC: Specification Language and Design Methodology 2000 Dordrecht, The Netherlands Kluwer Academic Publishers
2. Gajski D. D., Vahid F., Narayan S., Gong J., Specification and Design of Embedded Systems 1994 Upper Saddle River, NJ, USA Prentice Hall
3. Coste P., Hessel F., Le Marrec Ph., Multilanguage design of heterogeneous systems Proceedings of the 7th International Workshop on Hardware/Software Codesign (CODES 99) May 1999 Rome, Italy 54 58
4. Gerin P., Yoo S., Nicolescu G., Jerraya A. A., Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 01) January-February 2001 Yokohama, Japan 63 68
5. ModelSim SE Users Manual. Mentor Graphics Corp
6. Buck J., Ha S., Lee E. A., Messerschmitt D. G., Ptolemy: a framework for simulating and prototyping heterogeneous systems International Journal of Computer Simulation 1994 4 2 155 182
7. Grtker T., Liao S., Martin G., Swan S., System Design with SystemC 2002 Dordrecht, The Netherlands Kluwer Academic Publishers
8. Aubury M., Page I., Randall G., Saul J., Watts R., Handel-C language reference guide August 1996 Oxford, UK Oxford University Computing Laboratory
9. Ghenassia F., Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems 2005 New York, NY, USA Springer
10. sterling A., Brenner T., Ernst R., Herrmann D., Scholz T., Ye W., Staunstrup J., Wolf W., The COSYMA system Hardware/Software Co-Design: Principles and Practice 1997 Dordrecht, The Netherlands Kluwer Academic Publishers
11. Valderrama C. A., Romdhani M., Daveau J.-M., Marchioro G. F., Changuel A., Jerraya A. A., Staunstrup J., Wolf W., Cosmos: a transformational co-design tool for multiprocessor architectures Hardware/Software Co-Design: Principles and Practice 1997 Dordrecht, The Netherlands Kluwer Academic Publishers
12. Balarin F., Chiodo M., Giusto P., Hardware-Software Co-Design of Embedded Systems: The POLIS Approach 1997 Dordrecht, The Netherlands Kluwer Academic Publishers
13. Vanmeerbeeck G., Schaumont P., Vernalde S., Engels M., Bolsens I., Hardware/software partitioning for embedded systems in OCAPI-xl Proceedings of the International Symposium on Hardware-Software Codesign (CODES 01) April 2001 Copenhagen, Denmark
14. Schaumont P., Vernalde S., Rijnders L., Engels M., Bolsens I., A programming environment for the design of complex high speed ASICs Proceedings of the 35th Annual Conference on Design Automation (DAC 98) June 1998 San Francisco, Calif, USA 315 320
15. Grttner K., Oppenheimer F., Nebel W., Fouilliart A.-M., Colas-Bigey F., SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder Proceedings of the Design, Automation and Test in Europe Conference (DATE 08) March 2008 Munich, Germany 128 133
16. Cesrio W. O., Lyonnard D., Nicolescu G., Multiprocessor SoC platforms: a component-based design approach IEEE Design and Test of Computers 2002 19 6 52 63
17. Lyonnard D., Yoo S., Baghdadi A., Jerraya A. A., Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip Proceedings of the 38th Annual Conference on Design Automation (DAC 01) June 2001 Las Vegas, Nev, USA 518 523
18. van Rompaey K., Bolsens I., De Man H., Verkest D., CoWarea design environment for heterogeneous hardware/software systems Proceedings of the European Design Automation Conference (EURO-DAC 96) September 1996 Geneva, Switzerland 252 257
19. Klingauf W., Gdke H., Gnzel R., TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC 1 Proceedings of the Design, Automation and Test in Europe Conference (DATE 06) March 2006 Munich, Germany
20. Kempf T., Doerper M., Leupers R., A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms 2 Proceedings of the Design, Automation and Test in Europe Conference (DATE 05) March 2005 Munich, Germany 876 881
21. Balarin F., Watanabe Y., Hsieh H., Lavagno L., Passerone C., Sangiovanni-Vincentelli A., Metropolis: an integrated electronic system design environment Computer 2003 36 4 45 52
22. Sangiovanni-Vincentelli A. L., Quo vadis SLD: reasoning about trends and challenges of system-level design Proceedings of the IEEE 2007 95 3 467 506
23. Abdi S., Peng J., Yu H., System-on-chip environment (SCE version 2.2.0 beta): tutorial July 2003 CECS-TR-03-41 Irvine, Calif, USA Center for Embedded Computer Systems, University of California
24. Cai L., Gerstlauer A., Gajski D., Retargetable profiling for rapid, early system-level design space exploration Proceedings of the 41st Annual Conference on Design Automation (DAC 04) June 2004 San Diego, Calif, USA 281 286
25. Abdi S., Gajski D., Verification of system level model transformations International Journal of Parallel Programming 2006 34 1 29 59
26. Gerstlauer A., Cai L., Shin D., Yu H., Peng J., Dmer R., SCE database reference manual, version 2.2.0 beta July 2003 Irvine, Calif, USA Center for Embedded Computer Systems, University of California
27. Peng J., Gajski D., Optimal message-passing for data coherency in distributed architecture Proceedings of the 15th International Symposium on System Synthesis October 2002 Kyoto, Japan 20 25
28. Gerstlauer A., Yu H., Gajski D. D., Rtos modeling for system level design Proceedings of the Design, Automation and Test in Europe Conference (DATE 03) March 2003 Munich, Germany
29. Gerstlauer A., Shin D., Peng J., Dmer R., Gajski D. D., Automatic layer-based generation of system-on-chip bus communication models IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2007 26 9 1676 1687
30. Shin D., Gerstlauer A., Dmer R., Gajski D. D., An interactive design environment for C-based high-level synthesis of RTL processors IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2008 16 4 466 475
31. Yu H., Dmer R., Gajski D., Embedded software generation from system level design languages Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 04) January 2004 Yokohama, Japan 463 468
32. CECS eNews Volume 7, Issue 3, Center for Embedded Computer Systems, University of California, Irvine, Calif, USA, July 2007, http://www.cecs.uci. edu/enews/CECSeNewsJul07.pdf