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Volumn , Issue , 2003, Pages 1168-1169

SAT-based techniques in system synthesis

Author keywords

[No Author keywords available]

Indexed keywords

BINDING PROBLEM; BOOLEAN FORMULAE; BOOLEAN SATISFIABILITY PROBLEMS; DESIGN SPACE EXPLORATION; ELECTRONIC SYSTEMS; PROBLEM INSTANCES; QUANTIFIED BOOLEAN FORMULAS; SYSTEM SYNTHESIS;

EID: 50249155492     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253784     Document Type: Conference Paper
Times cited : (21)

References (3)
  • 1
    • 0031704808 scopus 로고    scopus 로고
    • System-level synthesis using evolutionary algorithms
    • R. Gupta, editor Kluwer, Jan
    • T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23-62. Kluwer, Jan. 1998
    • (1998) Design Automation for Embedded Systems , vol.3 , pp. 23-62
    • Blickle, T.1    Teich, J.2    Thiele, L.3
  • 3
    • 0034848823 scopus 로고    scopus 로고
    • Checking equivalence for partial implementations
    • Las Vegas, USA
    • C. Scholl and B. Becker. Checking Equivalence for Partial Implementations. In Proc. of 38th Design Automation Conference, pages238-243, Las Vegas, USA, 2001
    • (2001) Proc. of 38th Design Automation Conference , pp. 238-243
    • Scholl, C.1    Becker, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.