The dawn of predictive chip yield design: Along and beyond the memory lane

IEEE Design and Test of Computers

Volumn 27, Issue 6, 2010, Pages 36-45

  Joshi, Rajiv ^a   Kanj, Rouwaida ^b   Pelella, Anthony ^c   Tuminaro, Arthur ^c   Chan, Yuen ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM   (United States)

Author keywords

design and test; DFM; logic; memory; test; variation tolerant designs; yield

Indexed keywords

DESIGN AND TESTS; DFM; LOGIC; MEMORY; TEST; VARIATION-TOLERANT DESIGNS; YIELD;

LOGIC DESIGN; MONTE CARLO METHODS; STATIC RANDOM ACCESS STORAGE;

LOGIC CIRCUITS;

EID: 78650066569     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2010.95     Document Type: Article

References (12)

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