NoC-aware cache design for chip multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 565-566

  Abousamra, Ahmed K ^a   Melhem, Rami G ^a   Jones, Alex K ^b  

^a University of Pittsburgh   (United States)

^b PA 15260   (United States)

Author keywords

cache; CMP; network on chip; NoC

Indexed keywords

NETWORK-ON-CHIP; PARALLEL ARCHITECTURES;

CACHE; CACHE DESIGN; CHIP MULTI-PROCESSORS (CMPS); CHIP MULTIPROCESSOR; COMMUNICATION LOCALITY; DATA ACCESS; ON CHIP INTERCONNECT;

INTEGRATED CIRCUIT DESIGN;

EID: 78149272413     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854354     Document Type: Conference Paper

References (8)

1. A. Abousamra, R. Melhem, and A. K. Jones.Winning with pinning in NoC. In Proc. of Hot Interconnects (HOTI), 2009.
2. I. Artundo, W. Heirman, M. Loperena, C. Debaes, J. V. Campenhout, and H. Thienpont. Low-power reconfigurable network architecture for on-chip photonic interconnects. High-Performance Interconnects, Symposium on, 0:163-169, 2009.
3. J. Chang and G. S. Sohi. Cooperative caching for chip multiprocessors. In ISCA, pages 264-276, 2006.
4. Z. Guz, I. Keidar, A. Kolodny, and U. C. Weiser. Utilizing shared data in chip multiprocessors with the nahalal architecture. In SPAA, pages 1-10, 2008.
5. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Reactive nuca: near-optimal block placement and replication in distributed caches. In ISCA, pages 184-195, 2009.
6. J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S. W. Keckler. A nuca substrate for flexible cmp cache sharing. In ICS, pages 31-40, 2005.
7. N. D. E. Jerger, L.-S. Peh, and M. H. Lipasti. Circuit-switched coherence. In NOCS, pages 193-202, 2008.
8. J. Kim, J. D. Balfour, andW. J. Dally. Flattened butterfly topology for on-chip networks. In MICRO, pages 172-182, 2007.