-
2
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Proc. 23rd Int'l Symp. Computer Architecture, 1996.
-
(1996)
Proc. 23rd Int'l Symp. Computer Architecture
-
-
Tullsen, D.1
Eggers, S.2
Emer, J.3
Levy, H.4
Lo, J.5
Stamm, R.6
-
3
-
-
0001087280
-
Hyper-threading technology architecture and microarchitecture
-
D. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. Miller, and M. Upton, "Hyper-Threading Technology Architecture and Microarchitecture" , Intel Technology J., vol. 6, no. 1, pp. 4-15, 2002.
-
(2002)
Intel Technology J.
, vol.6
, Issue.1
, pp. 4-15
-
-
Marr, D.1
Binns, F.2
Hill, D.3
Hinton, G.4
Koufaty, D.5
Miller, J.6
Upton, M.7
-
4
-
-
78149248747
-
-
http://www.specbench.org/, 2010.
-
(2010)
-
-
-
5
-
-
47249121916
-
FAME: FAirly MEasuring multithreaded architectures
-
J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero, "FAME: FAirly MEasuring Multithreaded Architectures", Proc. 16th Int'l Conf. Parallel Architectures and Compilation Techniques, 2007.
-
(2007)
Proc. 16th Int'l Conf. Parallel Architectures and Compilation Techniques
-
-
Vera, J.1
Cazorla, F.2
Pajuelo, A.3
Santana, O.J.4
Fernández, E.5
Valero, M.6
-
8
-
-
21644443801
-
Dynamically controlled resource allocation in SMT processors
-
F. Cazorla, E. Fernandez, A. Ramirez, and M. Valero, "Dynamically Controlled Resource Allocation in SMT Processors", Proc. 37th Int'l Symp. Microarchitecture, 2004.
-
(2004)
Proc. 37th Int'l Symp. Microarchitecture
-
-
Cazorla, F.1
Fernandez, E.2
Ramirez, A.3
Valero, M.4
-
9
-
-
21644481490
-
Balanced multithreading: Increasing throughput via a low cost multithreading hierarchy
-
E. Tune, R. Kumar, D. Tullsen, and B. Calder, "Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy", Proc. 37th Int'l Symp. Microarchitecture, 2004.
-
(2004)
Proc. 37th Int'l Symp. Microarchitecture
-
-
Tune, E.1
Kumar, R.2
Tullsen, D.3
Calder, B.4
-
10
-
-
84981164301
-
Boosting SMT performance by speculation control
-
K. Luo, M. Franklin, S. Mukherjee, and A. Seznec, "Boosting SMT Performance by Speculation Control", Proc. 17th Int'l Parallel and Distributed Processing Symp., 2003.
-
(2003)
Proc. 17th Int'l Parallel and Distributed Processing Symp.
-
-
Luo, K.1
Franklin, M.2
Mukherjee, S.3
Seznec, A.4
-
11
-
-
84944403811
-
Single ISA heterogeneous multi-core architectures: The potential for processor power reduction
-
R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen, "Single ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction", Proc. 36th Int'l Symp. Microarchitecture, 2003.
-
(2003)
Proc. 36th Int'l Symp. Microarchitecture
-
-
Kumar, R.1
Farkas, K.2
Jouppi, N.3
Ranganathan, P.4
Tullsen, D.5
-
12
-
-
25844437046
-
POWER5 system microarchitecture
-
B. Sinharoy, R. Kalla, J. Tendler, R. Eickemeyer, and J. Joyner, "POWER5 System Microarchitecture", IBM J. of Research and Development, vol. 49, no. 4, pp. 505-521, 2005.
-
(2005)
IBM J. of Research and Development
, vol.49
, Issue.4
, pp. 505-521
-
-
Sinharoy, B.1
Kalla, R.2
Tendler, J.3
Eickemeyer, R.4
Joyner, J.5
-
13
-
-
78149264215
-
-
http://opensparc-t1.sunsource.net/, 2010.
-
(2010)
-
-
-
14
-
-
47249094055
-
System-level performance metrics for multiprogram workloads
-
May
-
S. Eyerman and L. Eeckhout, "System-Level Performance Metrics for Multiprogram Workloads", IEEE Micro, vol. 28, no. 3, pp. 42-53, May 2008.
-
(2008)
IEEE Micro
, vol.28
, Issue.3
, pp. 42-53
-
-
Eyerman, S.1
Eeckhout, L.2
|