Performance characteristics of scaled bilayer graphene pseudospin devices

IEEE Transactions on Electron Devices

Volumn 57, Issue 11, 2010, Pages 3059-3067

  Gilbert, M J ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Beyond complementary metaloxidesemiconductor (CMOS); bilayer; graphene; nanoelectronics; tunneling

Indexed keywords

ACHIEVABLE PERFORMANCE; ANALYTICAL PREDICTIONS; BEYOND COMPLEMENTARY METALOXIDESEMICONDUCTOR (CMOS); BI-LAYER; BI-LAYER STRUCTURE; DESIGN PARAMETERS; DEVICE PERFORMANCE; FERMI ENERGY; INTERLAYER INTERACTIONS; LAYER WIDTH; OPTIMAL DEVICES; PERFORMANCE CHARACTERISTICS; POST-CMOS; PSEUDOSPIN; QUANTUM INTERFERENCE; QUASIPARTICLES; TUNNELING;

LOGIC DEVICES; MONOLAYERS; NANOELECTRONICS;

GRAPHENE;

EID: 78049308470     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2065807     Document Type: Article

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