Bilayer pseudospin field-effect transistor: Applications to boolean logic

IEEE Transactions on Electron Devices

Volumn 57, Issue 4, 2010, Pages 755-764

  Reddy, Dharmendar ^a   Register, Leonard Franklin ^a   Tutuc, Emanuel ^a   Banerjee, Sanjay K ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Beyond complementary metal oxidesemiconductor (CMOS) graphene; Bilayer; Graphene; Nanoelectronics; Pseudospin; Tunneling

Indexed keywords

BEYOND COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) GRAPHENE; BILAYER; BOOLEAN LOGIC; INVERTER-BASED; MEMORY ELEMENT; NOR GATES; POWER CONSUMPTION; PSEUDOSPIN; ROOM-TEMPERATURE OPERATION; TUNNELING; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; GRAPHENE; NANOELECTRONICS; TUNNELING (EXCAVATION); WIND TUNNELS;

GRAPHITE;

EID: 77950295990     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2041280     Document Type: Article

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