Membership test logic for delay-insensitive codes

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 194-204

  Piestrak, Stanislaw J ^a,b  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b UNIVERSITÉ DE RENNES 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CODES (SYMBOLS); DELAY CIRCUITS; DETECTOR CIRCUITS;

ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS CIRCUITS AND SYSTEMS; ASYNCHRONOUS SYSTEM; DETECTION CIRCUITS; MULTI-OUTPUT; SHARP CONTRAST; SIMILAR DESIGN; THRESHOLD CIRCUITS;

COMPUTER CIRCUITS;

EID: 33749616495     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666505     Document Type: Conference Paper

References (32)

1. S. Hauck,\Asynchronous design methodologies, " Proc. IEEE, vol. E83, pp. 69-93, Jan. 1995.
2. A. J. Martin, "The limitations to delay-insensitivity in asynchronous circuits, " in Proc. Conference on Advanced Research in VLSI: 6th MIT Conf., C. Sfiequin, Ed., MIT Press, Cam-bridge, MA, 1990, pp. 263-278.
3. V. I. Varshavsky (Ed.), Self-Timed Control of Con-current Processes, Kluwer Acad. Publ., Norwell, MA, 1990 (Russian edition 1986), ch. 3.
4. O. A. Izosimov, et al., "Physical approach to CMOS self-timing, " Electron. Letters, vol. 26, pp. 1835-1836, 1990.
5. M. E. Dean, et al., "Self-timed logic using current-sensing completion detection (CSCD), " J. of VLSI Signal Proc., vol. 7, pp. 7-16, No. 1, 1994.
6. E. Grass, V. Bartlett, I. Kale,\Completion-detection techniques for asynchronous circuits, " IEICE Trans. Inf., Syst., vol. E80-D, pp. 344-350, March 1997.
7. V. Akella, N. H. Vaidya, G. R. Redinbo, "Limitations of VLSI implementation of delay-insensitive codes, " in Dig. Pap. 26th Int. Symp. on Fault-Tolerant Computing, Sendai, Japan, June 25-27, 1996, pp. 208-217.
8. D. B. Armstrong, et al., "Design of asynchronous circuits assuming unbounded gate delays, " IEEE Trans. Comput., vol. C-18, pp. 1110-1120, Dec. 1969.
9. A. J.Martin, et al., "The design of an asynchronous microprocessor, " in Proc. 1989 Decennial Caltech Conf., C. Sfiequin, Ed., MIT Press, Cambridge, MA, 1989, pp. 351-373.
10. T. Nanya, et al.,\TITAC: Design of a quasi-delay-insensitive microprocessor, " IEEE Design and Test, Sp. Issue on Asynchronous Circuits and Systems, vol. 11, pp. 50-63, No. 2, 1994.
11. I. David, R. Ginosar, M. Yoeli, "Implement-ing sequential machines as self-timed circuits, " IEEE Trans. Comput., vol. 41, pp. 12-17, Jan. 1992.
12. S. J. Piestrak and T. Nanya, "Towards totally self-checking delay-insensitive systems, " in Dig. Pap. 25th Int. Symp. on Fault-Tolerant Comput-ing, Pasadena, CA, June 27-30, 1995, pp. 228-237.
13. J. M. Berger, "A note on error detection codes for asymmetric binary channels, " Inform. Contr., vol. 4, pp. 68-73, Mar. 1961.
14. C. V. Freiman, "Optimal error detection codes for completely asymmetric binary channels, " Inform. Contr., vol. 5, pp. 64-71, Mar. 1962.
15. M. J. Ashjaee and S. M. Reddy, On totally self-checking checkers for separable codes, " IEEE Trans. Comput., vol. C-26, pp. 737-744, Aug. 1977.
16. J. E. Smith, "The design of totally self-checking check circuits for a class of unordered codes, " J. Des. Autom. Fault-Tolerant Comput., vol. 2, pp. 321-342, Oct. 1977.
17. G. P. Mak, J. A. Abraham, E. S. Davidson, "The design of PLAs with concurrent error detec-tion, " in Dig. Pap. 12th Int. FTC Symp., Santa Monica, CA, June 1982, pp. 303-310.
18. M. Blaum (Ed.), Unidirectional Error Control Codes, IEEE Press, 1992.
19. V. I. Varshavsky, et al., "Possibility of imple-menting an asynchronous interface using a self-synchronizing code with identifier, " Autom. Contr. Comput. Sci., vol. 15, pp. 77-81, No. 5, 1981.
20. J. E. Smith, "On separable unordered codes, " IEEE Trans. Comput., vol. C-33, pp. 741-743, Aug. 1984.
21. T. Verhoefi, "Delay-insensitive codes|An overview, " Distr. Computing, vol. 3, pp. 1-8, No. 1, 1988.
22. S. J. Piestrak, "Design of TSC code-disjoint inverter-free 4 for separable unordered codes, " in Proc. ICCD'94, Int. Conf. on Computer Design: VLSI in Computers & Processors, Cambridge, MA, Oct. 10-12, 1994, pp. 128-131.
23. K. E. Batcher, "Sorting networks and their ap-plications, " in Proc. 1968 SJCC, AFIPS, vol. 32, 1968, pp. 307-314.
24. D. E. Knuth, "The Art of Computer Program-ming, Vol. III, Sorting and Searching, " 2nd Ed., Reading, MA, Addison-Wesley, 1973, ch. 5.
25. D. C. Van Voorhis, "An economical construction for sorting networks, " in Proc. AFIPS NCC, 1974, pp. 921-927.
26. R. L. (Scot) Drysdale and F. H. Young, "Improved divide/sort/merge sorting networks, " SIAM J. Comput., vol. 4, pp. 264-270, Sept. 1975.
27. E. A. Lamagna, "The complexity of monotone networks for certain bilinear forms, routing prob-lems, sorting, merging, " IEEE Trans. Com-put., vol. C-28, pp. 773-782, Oct. 1979.
28. S. J. Piestrak, "The minimal test set for sort-ing networks and the use of sorting networks in self-testing checkers for unordered codes, " in Dig. Pap. 20th Int. Symp. on Fault-Tolerant Comput-ing, Newcastle upon Tyne, UK, June 26-28, 1990, pp. 467-474.
29. S. J. Piestrak, "The minimal test set for multi-output threshold circuits implemented as sorting networks, " IEEE Trans. Comput., vol. 42, pp. 700-712, June 1993.
30. S. J. Piestrak, Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Scientific Papers of the Inst. of Techn. Cybern. of the Techn. Univ. of Wroc law, No. 92, Ser.: Monographs No. 24, Oficyna Wyd. Polit. Wroc l., Wroc law 1995.
31. M. Blaum and J. Bruck,\Coding for skew-tolerant parallel 0 communications, " IEEE Trans. Inform. Theory., vol. 39, pp. 379-388, Mar. 1993.
32. M. Blaum and J. Bruck,\Delay-insensitive pipelined communication on parallel buses, " IEEE Trans. Comput., vol. 44, pp. 660-668, May 1995.