Limitations of VLSI implementation of delay-sensitive codes

Proceedings - Annual International Conference on Fault-Tolerant Computing

Volumn , Issue , 1996, Pages 208-217

  Akella, Venkatesh ^a   Vaidya, Nitin H ^a   Redinbo, G Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); CODING ERRORS; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; DATA HANDLING; ERROR CORRECTION; ERROR DETECTION; FORMAL LOGIC; VLSI CIRCUITS;

ASYNCHRONOUS DECODERS; DELAY INSENSITIVE (DI) CODES;

DECODING;

EID: 0029725038     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)