Using partial orders for trace theoretic verification of asynchronous circuits

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 152-163

  Yoneda, T ^a   Yoshikawa, T ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; CONFORMANCE CHECKING; LIVENESS PROPERTIES; PARTIAL ORDER; REDUCED-STATE; STATE REDUCTION ALGORITHM; STATE-SPACE REDUCTION; TRACE THEORETIC VERIFICATION;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84969373200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494447     Document Type: Conference Paper

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