A new asynchronous pipeline scheme: Application to the design of a self-timed ring divider

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 1001-1013

  Renaudin, Marc ^a,c,d   El Hassan, Bachar ^a,c,e,f   Guyot, Alain ^b,c,g,h  

^a ORANGE LABS   (France)

^b TIMA LABORATORY   (France)

^c GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^d ECOLE DES MINES DE NANTES   (France)

^e UNIVERSITY OF TRIPOLI   (Libyan Arab Jamahiriya)

^f LEBANESE UNIVERSITY   (Lebanon)

^g STANFORD UNIVERSITY   (United States)

^h Institut National Polytechnique

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOGIC DESIGN; NETWORK PROTOCOLS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS PIPELINE SCHEME; CHIP ARCHITECTURE; DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC; PRIVATE ASYNCHRONOUS STANDARD CELL LIBRARY; SELF TIMED RING DIVIDER;

DIVIDING CIRCUITS (ARITHMETIC);

EID: 0030191609     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508214     Document Type: Article

References (46)

1. C. H. Erdelyi, W. R. Griffin, and R. D. Kilmoyer, "Cascode voltage switch logic design," VLSI Design, pp. 78-86, Oct. 1984.
2. C. Y. Wu and K. H. Cheng, "Latched CMOS differential logic (LCDL) for complex high-speed VLSI," IEEE J. Solid-State Circuits, vol. 26, no. 9, pp. 1324-1328, Sept. 1991.
3. C. Heer, "Entwurfsmethode für Selbstgetaktete VLSI-Datenpfadarchitekturen," Ph.D. dissertation, Verlag Shaker, Ulm University, Aug. 1995.
4. IEEE Design and Test of Computers, vol. 11, no. 2, Summer 1994.
5. IEEE Design and Test of Computers, vol. 11, no. 3, Fall 1994.
6. W. Wayt Gibbs, "Turning back the clock," Sci. Amer., pp. 40, June 1995.
7. S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, no. 1, pp. 69-93, Jan. 1995.
8. G. Birtwistle and A. Davis, Eds., Asynchronous Digital Circuit Design. New York: Springer, 1995.
9. A. Martin, "Synthesis of asynchronous VLSI circuits," Caltech-CS-TR-93-28.
10. J. VLSI Signal Processing, Special Issue: Circuit Design for VLSI Signal Processing, vol. 7, no. 1/2, Feb. 1994.
11. V. Akella and G. Gopalakrishnan, "Shilpa: A high-level synthesis system for self-timed circuits," presented at Int. Conf. Computer Aided Design (ICCAD), Santa Clara, Nov. 1992.
12. K. Van Berkel, Handshake Circuits - An Asynchronous Architecture For VLSI Programming. Cambridge, U.K.: Cambridge University Press, 1993.
13. T. H. Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, "Automatic synthesis of asynchronous circuits from high level specification," IEEE Trans. Computer-Aided Design, vol. 8, no. 11, pp. 1185-1205, Nov. 1989.
14. T. H. Meng, Synchronization Design for Digital Systems. New York: Kluwer, 1991.
15. J. Yaun, I. Karlsson, and C. Svensson, "A true single phase clock dynamic CMOS circuit technique," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 899-901, Oct. 1987.
16. J. Yaun and C. Svensson, "High speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
17. I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, June 1989.
18. T. E. Williams, "Self timed rings and their application to division," Ph.D. dissertation, Stanford University, Stanford, CA, May 1991
19. Y. K. Tan and Y. C. Lim, "Self timed precharge latch," in Proc. ISCAS 90, pp. 566-569.
20. K. M. Chu and D. L. Pulfrey, "A comparison of CMOS techniques: Differential cascode voltage switch logic versus conventional logic," IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528-532, Aug. 1987.
21. C. D. Nielsen, "Evaluation of function blocks for asynchronous design," in EURODAC'94, Grenoble, France, Sept. 1994, pp. 454-459.
22. T. H. Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, "Design of clock-free asynchronous systems for real-time signal processing," in ICASSP 89, pp. 2532-2535.
23. G. M. Jacob and R. W. Brodersen, "A fully asynchronous digital signal processor using self-timed circuits," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 526-1537, Dec. 1990.
24. M. Renaudin and B. El Hassan, "A minimum power, 100 MHz, 12 × 18 + 30-b multiplier-accumulator operating in asynchronous and synchronous mode," presented at ESSCIRC 94, Ulm, Germany, Sept. 1994.
25. J. M. Rabaey, "Low power digital design," in Circuits Systems Tutorials, IEEE ISCAS 94, C. Toumazou, Ed., London, U.K., June 1994, pp. 373-386.
26. O. Salomon and H. Klar, "Self-timed fully pipelined multipliers," in Asynchronous Design Methodologies IFIP Workshop (A-28), S. Furber and M. Edwards, Eds. Amsterdam, The Netherlands: North-Holland-Elsevier, 1993, pp. 45-55.
27. U. V. Cummings, A. M. Lines, and A. J. Martin, "An asynchronous pipelined lattice structure filter," in Proc. Int. Symp. Advanced Res. Asynchronous Circuits and Systems, Salt Lake City, UT, Nov. 3-5, 1994, pp. 126-133.
28. T. E. Williams, "Performance of iterative computation in self timed rings," in J. VLSI Signal Processing, no. 7, pp. 17-31, Feb. 1994.
29. G. Privat, F. Robin, M. Renaudin, and B. El Hassan, "A fine-grain asynchronous VLSI cellular array processor architecture," in Proc. ISCAS 95, Seattle, June 1995, pp. II.1041-II.1044.
30. K. M. Chu and D. Pulfrey, "Design procedures for differential cascode voltage switch circuits," IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1082-1087, Dec. 1986.
31. C. Ykman-Couvreur, B. Lin, G. Goosens, and H. De Man, "Synthesis and optimization of asynchronous controllers based on extended lock graph theory," presented at Proc. European Design Automation Conf., Feb. 1993.
32. L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits. New York: Kluwer, 1993.
33. M. A. Kishinevsky, A. K. Kondratyev, A. R. Taubin, and V. I. Varshavsky, Concurrent Hardware, the Theory and Practice of Self-Timed Design. Chichester: Wiley Series in Parallel Computing, 1994.
34. B. El Hassan, A. Guyot, M. Renaudin, and V. Levering, "New self timed ring and their application to division and square root extraction," in Proc. ESSCIRC'95, Lille, France, Sept. 1995, pp. 226-229.
35. M. Renaudin and B. El Hassan, "The design of fast asynchronous adders and their implementation using DCVSL logic," in Proc. ISCAS 94, London, UK, May 1994, pp. IV.291-IV.294.
36. A. Avizienis, "Signed number representation for fast parallel arithmetic," IRE Trans. Electron. Comput., vol. EC-10, Sept. 1961.
37. J. E. Robertson, "The correspondence between methods of digital division and multiplier recoding procedures," IEEE Trans. Comput., vol. C-19, no. 8, Aug. 1970.
38. K. D. Tocher, "Techniques of multiplication and division for automatic binary computers," Quart. J. Mech. Appl Math., vol. 11 no. 3, 1958.
39. J. William and V. C. Hamacher, "A linear-time divider array," Canadian Elec. Eng. J., vol. 6, no. 4, 1981.
40. I. Moussa, A. Skaf, and A. Guyot, "Design of a GaAs redundant divider," presented at Proc. VLSI'93, Grenoble, France, Sept. 1993.
41. G. S. Taylor, "Radix 16 SRT divider with overlapped quotient selection stages," in Proc. 7th IEEE Symp. Computer Arithmetic, Urbana, IL, 1985, pp. 64-71.
42. T. E. Williams and M. Horowitz, "A zero overhead self-timed 160 ns 54 bits CMOS divider," IEEE J. Solid-State Circuits, vol. 26, pp. 1651-1661, Nov. 1991.
43. G. Matsubara, N. Ide, H. Tago, S. Suzuki, and N. Goto, "30-ns 55-b shared radix-2 division and square root using self timed circuit," in Proc. 12th IEEE Symp. Computer Arithmetic, Bath, U.K., 1995, pp. 98-105.
44. M. D. Ercegovac and T. Lang, "On-the-fly conversion of redundant into conventional representations," IEEE Trans. Comput., vol. C-36, no. 7, pp. 895-897, July 1987.
45. S. Majeski, "Square rooting algorithms for high speed digital circuits," IEEE Trans. Comput., vol. C-34, no. 8, pp. 724-733, Aug. 1985.
46. S. E. McQuillan and J. V. McCanny, "New algorithms and VLSI architectures for SRT division and square root," in Proc. 11th IEEE Symp. Computer Arithmetic, Windsor, Canada, 1993, pp. 80-86.