A low-power SRAM using bit-line charge-recycling for read and write operations

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 10, 2010, Pages 2173-2183

  Yang, Byung Do ^a  

^a Chungbuk National University   (South Korea)

Author keywords

Bit line; charge recycling; low power; low swing; SRAM

Indexed keywords

BIT LINES; CHARGE-RECYCLING; LOW POWER; LOW SWING; SRAM;

CMOS INTEGRATED CIRCUITS; RECYCLING;

STATIC RANDOM ACCESS STORAGE;

EID: 77957566714     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2063950     Document Type: Conference Paper

References (6)

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3. B.-D. Yang and L.-S. Kim, "A low-power SRAM using hierachical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol.40, no.6, pp. 1366-1376, Jun. 2005.
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6. M. Sharifkhni and M. Sachdev, "Segmented virtual ground architecture for low-power embedded SRAM," IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol.15, no.1, pp. 196-205, Feb. 2007.