SOC test architecture and method for 3-D ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 10, 2010, Pages 1645-1649

  Lo, Chih Yen ^a   Hsing, Yu Tsao ^a   Denq, Li Ming ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

3 D IC test; system on chip (SOC) test; test architecture; test integration

Indexed keywords

3-D IC TEST; 3-D ICS; 3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; BOND TEST; DATA APPLICATION; DESIGN-FOR-TESTABILITY METHODS; DIRECT ACCESS; SECURITY PROCESSOR; SOC TESTS; SYSTEM-ON-CHIP TEST; TEST ACCESS; TEST ARCHITECTURE; TEST CHIPS; TEST INTEGRATION; TEST TIME; THROUGH-SILICON VIA;

ACCESS CONTROL; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; ELECTRONICS PACKAGING; FORMAL METHODS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORK SECURITY; PROGRAMMABLE LOGIC CONTROLLERS; THREE DIMENSIONAL;

TESTING;

EID: 77957001498     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2051732     Document Type: Article

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