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Volumn 6, Issue 18, 2010, Pages 1974-1980

Vertical nanowire architectures: Statistical processing of porous templates towards discrete nanochannel integration

Author keywords

[No Author keywords available]

Indexed keywords

CONCEPTUAL FRAMEWORKS; CROSSBAR LATCHES; NANO CHANNELS; NANOPOROUS TEMPLATES; NANOWIRE GROWTH; PATTERNING APPROACHES; POROUS ALUMINA TEMPLATES; POROUS TEMPLATES; SELECTION RULES; STATISTICAL PROCESS; STATISTICAL PROCESSING; ULTRADENSE;

EID: 77956903183     PISSN: 16136810     EISSN: 16136829     Source Type: Journal    
DOI: 10.1002/smll.201000723     Document Type: Article
Times cited : (5)

References (41)
  • 31
    • 77956914382 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors
    • International Technology Roadmap for Semiconductors, http://www.itrs.net/ Links/2007ITRS/Home2007.html.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.