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Volumn 97, Issue 11, 2010, Pages

Effective reduction of interfacial traps in Al2 O 3/GaAs (001) gate stacks using surface engineering and thermal annealing

(11) Chang, Y C a,b Merckling, C c Penaud, J d Lu, C Y b Wang, W E c Dekoster, J c Meuris, M c Caymax, M c Heyns, M b,c Kwo, J a,e Hong, M a

a NATIONAL TSING HUA UNIVERSITY (Taiwan)

b UNIVERSITY OF LEUVEN (Belgium)

c IMEC (Belgium)

d Riber ^* (France)

e NATIONAL TAIWAN UNIVERSITY (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONDUCTANCE METHOD; GAAS; GAAS(001); GATE STACKS; IN-SITU DEPOSITION; INTERFACIAL STATE DENSITY; INTERFACIAL TRAPS; METAL-OXIDE-SEMICONDUCTOR CAPACITORS; P-TYPE; POST DEPOSITION ANNEALING; RECONSTRUCTED SURFACES; SURFACE ENGINEERING; THERMAL-ANNEALING;

ANNEALING; EPITAXIAL GROWTH; GALLIUM ARSENIDE; MOLECULAR BEAM EPITAXY; MOLECULAR BEAMS; SEMICONDUCTING GALLIUM;

GALLIUM ALLOYS;

EID: 77956850242 PISSN: 00036951 EISSN: None Source Type: Journal
DOI: 10.1063/1.3488813 Document Type: Article

Times cited : (63)

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