Low-power logic styles for full-adder circuits

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2001, Pages 1417-1420

  Quintana, J M ^a   Avedillo, M J ^a   Jimenez R ^a   Rodriguez Villegas, E ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; CURVE FITTING; DELAY CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC CIRCUITS; TIMING CIRCUITS;

CMOS DESIGN; LOW VOLTAGES; LOW-POWER LOGIC; MINIMUM DELAY; OPTIMAL POWER; POWER DELAY PRODUCT; STATISTICAL OPTIMIZATION; SUPPLY VOLTAGES;

LOW POWER ELECTRONICS;

EID: 77956790947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icecs.2001.957480     Document Type: Conference Paper

References (10)

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