Area efficient time-shared FIR filters in nanoscale CMOS

1st International Conference on Green Circuits and Systems, ICGCS 2010

Volumn , Issue , 2010, Pages 54-59

  Michael, Navin ^a   Vinod, A P ^a   Moy, Christophe ^b   Palicot, Jacques ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b IETR   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL TRANSFORMATION; AREA EFFICIENT; AREA PENALTY; DOMINANT MODE; DYNAMIC POWER; DYNAMIC POWER CONSUMPTION; FILTER ALGORITHM; HIGHER-DEGREE; LEAKAGE POWER; LOW-POWER DESIGN; NANOSCALE CMOS; POWER CONSUMPTION; STRENGTH REDUCTION; TIMING SLACK;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; NANOSTRUCTURED MATERIALS; TIME MEASUREMENT; TIMING CIRCUITS;

FIR FILTERS;

EID: 77956561435     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICGCS.2010.5543098     Document Type: Conference Paper

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