Low power FIR filter implementations based on coefficient ordering algorithm

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 226-228

  Erdogan, A T ^a   Arslan, T ^a,b  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

^b INSTITUTE FOR SYSTEM LEVEL INTEGRATION   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DATA MEMORY; DSP SYSTEMS; POWER CONSUMPTION; TRANSPOSE DIRECT FORM (TDF);

CMOS INTEGRATED CIRCUITS; DATA RECORDING; GRAPHIC METHODS; MATHEMATICAL MODELS; MULTIPLEXING; POWER ELECTRONICS; RANDOM ACCESS STORAGE; SWITCHING; VOLTAGE MEASUREMENT;

FIR FILTERS;

EID: 4544299292     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339537     Document Type: Conference Paper

References (7)

1. I.S. Abu-Khater, A. Bellaouar, M.I. Elmasry: "Circuit Techniques for CMOS Low-Power High-Performance Multipliers", IEEE Journal of Solid-State Circuits, vol. 31, no. 10, pp. 1535-1546, Oct. 1996.
2. N. Sankarayya, K. Roy, D. Bhattacharya: "Algorithms for Low Power and High Speed FIR Filter Realisation Using Differential Coefficients", IEEE Trans. on Circuits and Systems-II, 1997, vol. 44, no. 6, pp. 488-497.
3. th Int. Conf. on VLSI Design, pp. 370-375, Jan. 1996.
4. J.T. Ludwig, S.H. Nawab, A.P. Chandrakasan: "Low Power Digital Filtering Using Approximate Processing", IEEE J. of Solid-State Circuits, vol. 31, pp. 395 399, Mar. 1996.
5. A.T. Erdogan and T. Arslan: "On the Low Power Implementation of FIR Filtering Structures on Single Multiplier DSPs", IEEE Trans. on Circuits and Systems II, vol. 49, no. 3, March 2002, pp. 223-229.
6. M. Mehendale, S.D. Sherlekar, G. Venkatesh: "Low-Power Realization of FIR Filters on Programmable DSPs", IEEE Trans. on VLSI Systems, vol.6, no.4, pp.546-553, Dec. 1998.
7. R. Fried: "Minimizing energy dissipation in high-speed multipliers", IEEE Symposium on Low Power Electronics and Design, ISLPED'97, pp. 214-219.